8( 2x"ti,omap3-evmti,omap3430ti,omap3 +7TI OMAP35XX EVM (TMDSEVM3530)chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+ *GdefaultU_pinmux_twl4030_pinsgA_pinmux_dss_dpi_pins2g_pinmux_mmc1_pinsPg "$&_pinmux_mmc2_pins0g(*,.02_pinmux_uart3_pinsgnAp_pinmux_ehci_port_select_pinsg_pinmux_hsusb2_pins0g      _pinmux_wl12xx_gpiogPN_pinmux_smsc911x_pinsg_scm_conf@270sysconsimple-busyp0+ p0_pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapy{pbias_mmc_omap2430pbias_mmc_omap2430w@-_clocks+mcbsp5_mux_fck@68ti,composite-mux-clock}yh_ mcbsp5_fckti,composite-clock} _mcbsp1_mux_fck@4ti,composite-mux-clock}y_ mcbsp1_fckti,composite-clock} _mcbsp2_mux_fck@4ti,composite-mux-clock} y_mcbsp2_fckti,composite-clock}_mcbsp3_mux_fck@68ti,composite-mux-clock} yh_mcbsp3_fckti,composite-clock}_mcbsp4_mux_fck@68ti,composite-mux-clock} yh_mcbsp4_fckti,composite-clock}_clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+ *pinmux_twl4030_vpins g_pinmux_dss_dpi_pins10g  _aes@480c5000 ti,omap3-aesaesyH PPABtxrxprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockY_osc_sys_ck@d40 ti,mux-clock}y @_sys_ck@1270ti,divider-clock}yp_ sys_clkout1@d70ti,gate-clock}y pdpll3_x2_ckfixed-factor-clock}'dpll3_m2x2_ckfixed-factor-clock}'_dpll4_x2_ckfixed-factor-clock}'corex2_fckfixed-factor-clock}'_!wkup_l4_ickfixed-factor-clock} '_Pcorex2_d3_fckfixed-factor-clock}!'_corex2_d5_fckfixed-factor-clock}!'_clockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clock_Bvirt_12m_ck fixed-clock_virt_13m_ck fixed-clock]@_virt_19200000_ck fixed-clock$_virt_26000000_ck fixed-clock_virt_38_4m_ck fixed-clockI_dpll4_ck@d00ti,omap3-dpll-per-clock} y D 0_dpll4_m2_ck@d48ti,divider-clock}?y H_"dpll4_m2x2_mul_ckfixed-factor-clock}"'_#dpll4_m2x2_ck@d00ti,gate-clock}#y 1_$omap_96m_alwon_fckfixed-factor-clock}$'_+dpll3_ck@d00ti,omap3-dpll-core-clock} y @ 0_dpll3_m3_ck@1140ti,divider-clock}y@_%dpll3_m3x2_mul_ckfixed-factor-clock}%'_&dpll3_m3x2_ck@d00ti,gate-clock}& y 1_'emu_core_alwon_ckfixed-factor-clock}''_dsys_altclk fixed-clock_0mcbsp_clks fixed-clock_dpll3_m2_ck@d40ti,divider-clock}y @_core_ckfixed-factor-clock}'_(dpll1_fck@940ti,divider-clock}(y @_)dpll1_ck@904ti,omap3-dpll-clock} )y  $ @ 4_dpll1_x2_ckfixed-factor-clock}'_*dpll1_x2m2_ck@944ti,divider-clock}*y D_>cm_96m_fckfixed-factor-clock}+'_,omap_96m_fck@d40 ti,mux-clock}, y @_Gdpll4_m3_ck@e40ti,divider-clock} y@_-dpll4_m3x2_mul_ckfixed-factor-clock}-'_.dpll4_m3x2_ck@d00ti,gate-clock}.y 1_/omap_54m_fck@d40 ti,mux-clock}/0y @_:cm_96m_d2_fckfixed-factor-clock},'_1omap_48m_fck@d40 ti,mux-clock}10y @_2omap_12m_fckfixed-factor-clock}2'_Idpll4_m4_ck@e40ti,divider-clock} y@_3dpll4_m4x2_mul_ckti,fixed-factor-clock}3GUb_4dpll4_m4x2_ck@d00ti,gate-clock}4y 1b_dpll4_m5_ck@f40ti,divider-clock}?y@_5dpll4_m5x2_mul_ckti,fixed-factor-clock}5GUb_6dpll4_m5x2_ck@d00ti,gate-clock}6y 1b_ldpll4_m6_ck@1140ti,divider-clock}?y@_7dpll4_m6x2_mul_ckfixed-factor-clock}7'_8dpll4_m6x2_ck@d00ti,gate-clock}8y 1_9emu_per_alwon_ckfixed-factor-clock}9'_eclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}(y p_;clkout2_src_mux_ck@d70ti,composite-mux-clock}( ,:y p_<clkout2_src_ckti,composite-clock};<_=sys_clkout2@d70ti,divider-clock}=@y pumpu_ckfixed-factor-clock}>'_?arm_fck@924ti,divider-clock}?y $emu_mpu_alwon_ckfixed-factor-clock}?'_fl3_ick@a40ti,divider-clock}(y @_@l4_ick@a40ti,divider-clock}@y @_Arm_ick@c40ti,divider-clock}Ay @gpt10_gate_fck@a00ti,composite-gate-clock}  y _Cgpt10_mux_fck@a40ti,composite-mux-clock}B y @_Dgpt10_fckti,composite-clock}CDgpt11_gate_fck@a00ti,composite-gate-clock}  y _Egpt11_mux_fck@a40ti,composite-mux-clock}B y @_Fgpt11_fckti,composite-clock}EFcore_96m_fckfixed-factor-clock}G'_mmchs2_fck@a00ti,wait-gate-clock}y _mmchs1_fck@a00ti,wait-gate-clock}y _i2c3_fck@a00ti,wait-gate-clock}y _i2c2_fck@a00ti,wait-gate-clock}y _i2c1_fck@a00ti,wait-gate-clock}y _mcbsp5_gate_fck@a00ti,composite-gate-clock} y _ mcbsp1_gate_fck@a00ti,composite-gate-clock} y _ core_48m_fckfixed-factor-clock}2'_Hmcspi4_fck@a00ti,wait-gate-clock}Hy _mcspi3_fck@a00ti,wait-gate-clock}Hy _mcspi2_fck@a00ti,wait-gate-clock}Hy _mcspi1_fck@a00ti,wait-gate-clock}Hy _uart2_fck@a00ti,wait-gate-clock}Hy _uart1_fck@a00ti,wait-gate-clock}Hy  _core_12m_fckfixed-factor-clock}I'_Jhdq_fck@a00ti,wait-gate-clock}Jy _core_l3_ickfixed-factor-clock}@'_Ksdrc_ick@a10ti,wait-gate-clock}Ky _gpmc_fckfixed-factor-clock}K'core_l4_ickfixed-factor-clock}A'_Lmmchs2_ick@a10ti,omap3-interface-clock}Ly _mmchs1_ick@a10ti,omap3-interface-clock}Ly _hdq_ick@a10ti,omap3-interface-clock}Ly _mcspi4_ick@a10ti,omap3-interface-clock}Ly _mcspi3_ick@a10ti,omap3-interface-clock}Ly _mcspi2_ick@a10ti,omap3-interface-clock}Ly _mcspi1_ick@a10ti,omap3-interface-clock}Ly _i2c3_ick@a10ti,omap3-interface-clock}Ly _i2c2_ick@a10ti,omap3-interface-clock}Ly _i2c1_ick@a10ti,omap3-interface-clock}Ly _uart2_ick@a10ti,omap3-interface-clock}Ly _uart1_ick@a10ti,omap3-interface-clock}Ly  _gpt11_ick@a10ti,omap3-interface-clock}Ly  _gpt10_ick@a10ti,omap3-interface-clock}Ly  _mcbsp5_ick@a10ti,omap3-interface-clock}Ly  _mcbsp1_ick@a10ti,omap3-interface-clock}Ly  _omapctrl_ick@a10ti,omap3-interface-clock}Ly _dss_tv_fck@e00ti,gate-clock}:y_dss_96m_fck@e00ti,gate-clock}Gy_dss2_alwon_fck@e00ti,gate-clock} y_dummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock} y _Mgpt1_mux_fck@c40ti,composite-mux-clock}B y @_Ngpt1_fckti,composite-clock}MNaes2_ick@a10ti,omap3-interface-clock}Ly _wkup_32k_fckfixed-factor-clock}B'_Ogpio1_dbck@c00ti,gate-clock}Oy _sha12_ick@a10ti,omap3-interface-clock}Ly _wdt2_fck@c00ti,wait-gate-clock}Oy _wdt2_ick@c10ti,omap3-interface-clock}Py _wdt1_ick@c10ti,omap3-interface-clock}Py _gpio1_ick@c10ti,omap3-interface-clock}Py _omap_32ksync_ick@c10ti,omap3-interface-clock}Py _gpt12_ick@c10ti,omap3-interface-clock}Py _gpt1_ick@c10ti,omap3-interface-clock}Py _per_96m_fckfixed-factor-clock}+'_ per_48m_fckfixed-factor-clock}2'_Quart3_fck@1000ti,wait-gate-clock}Qy _gpt2_gate_fck@1000ti,composite-gate-clock} y_Rgpt2_mux_fck@1040ti,composite-mux-clock}B y@_Sgpt2_fckti,composite-clock}RSgpt3_gate_fck@1000ti,composite-gate-clock} y_Tgpt3_mux_fck@1040ti,composite-mux-clock}B y@_Ugpt3_fckti,composite-clock}TUgpt4_gate_fck@1000ti,composite-gate-clock} y_Vgpt4_mux_fck@1040ti,composite-mux-clock}B y@_Wgpt4_fckti,composite-clock}VWgpt5_gate_fck@1000ti,composite-gate-clock} y_Xgpt5_mux_fck@1040ti,composite-mux-clock}B y@_Ygpt5_fckti,composite-clock}XYgpt6_gate_fck@1000ti,composite-gate-clock} y_Zgpt6_mux_fck@1040ti,composite-mux-clock}B y@_[gpt6_fckti,composite-clock}Z[gpt7_gate_fck@1000ti,composite-gate-clock} y_\gpt7_mux_fck@1040ti,composite-mux-clock}B y@_]gpt7_fckti,composite-clock}\]gpt8_gate_fck@1000ti,composite-gate-clock}  y_^gpt8_mux_fck@1040ti,composite-mux-clock}B y@__gpt8_fckti,composite-clock}^_gpt9_gate_fck@1000ti,composite-gate-clock}  y_`gpt9_mux_fck@1040ti,composite-mux-clock}B y@_agpt9_fckti,composite-clock}`aper_32k_alwon_fckfixed-factor-clock}B'_bgpio6_dbck@1000ti,gate-clock}by_gpio5_dbck@1000ti,gate-clock}by_gpio4_dbck@1000ti,gate-clock}by_gpio3_dbck@1000ti,gate-clock}by_gpio2_dbck@1000ti,gate-clock}by _wdt3_fck@1000ti,wait-gate-clock}by _per_l4_ickfixed-factor-clock}A'_cgpio6_ick@1010ti,omap3-interface-clock}cy_gpio5_ick@1010ti,omap3-interface-clock}cy_gpio4_ick@1010ti,omap3-interface-clock}cy_gpio3_ick@1010ti,omap3-interface-clock}cy_gpio2_ick@1010ti,omap3-interface-clock}cy _wdt3_ick@1010ti,omap3-interface-clock}cy _uart3_ick@1010ti,omap3-interface-clock}cy _uart4_ick@1010ti,omap3-interface-clock}cy_gpt9_ick@1010ti,omap3-interface-clock}cy _gpt8_ick@1010ti,omap3-interface-clock}cy _gpt7_ick@1010ti,omap3-interface-clock}cy_gpt6_ick@1010ti,omap3-interface-clock}cy_gpt5_ick@1010ti,omap3-interface-clock}cy_gpt4_ick@1010ti,omap3-interface-clock}cy_gpt3_ick@1010ti,omap3-interface-clock}cy_gpt2_ick@1010ti,omap3-interface-clock}cy_mcbsp2_ick@1010ti,omap3-interface-clock}cy_mcbsp3_ick@1010ti,omap3-interface-clock}cy_mcbsp4_ick@1010ti,omap3-interface-clock}cy_mcbsp2_gate_fck@1000ti,composite-gate-clock}y_mcbsp3_gate_fck@1000ti,composite-gate-clock}y_mcbsp4_gate_fck@1000ti,composite-gate-clock}y_emu_src_mux_ck@1140 ti,mux-clock} defy@_gemu_src_ckti,clkdm-gate-clock}g_hpclk_fck@1140ti,divider-clock}hy@pclkx2_fck@1140ti,divider-clock}hy@atclk_fck@1140ti,divider-clock}hy@traceclk_src_fck@1140 ti,mux-clock} defy@_itraceclk_fck@1140ti,divider-clock}i y@secure_32k_fck fixed-clock_jgpt12_fckfixed-factor-clock}j'wdt1_fckfixed-factor-clock}j'security_l4_ick2fixed-factor-clock}A'_kaes1_ick@a14ti,omap3-interface-clock}ky rng_ick@a14ti,omap3-interface-clock}ky sha11_ick@a14ti,omap3-interface-clock}ky des1_ick@a14ti,omap3-interface-clock}ky cam_mclk@f00ti,gate-clock}lybcam_ick@f10!ti,omap3-no-wait-interface-clock}Ay_csi2_96m_fck@f00ti,gate-clock}y_security_l3_ickfixed-factor-clock}@'_mpka_ick@a14ti,omap3-interface-clock}my icr_ick@a10ti,omap3-interface-clock}Ly des2_ick@a10ti,omap3-interface-clock}Ly mspro_ick@a10ti,omap3-interface-clock}Ly mailboxes_ick@a10ti,omap3-interface-clock}Ly ssi_l4_ickfixed-factor-clock}A'_tsr1_fck@c00ti,wait-gate-clock} y _ sr2_fck@c00ti,wait-gate-clock} y _ sr_l4_ickfixed-factor-clock}A'dpll2_fck@40ti,divider-clock}(y@_ndpll2_ck@4ti,omap3-dpll-clock} ny$@4_odpll2_m2_ck@44ti,divider-clock}oyD_piva2_ck@0ti,wait-gate-clock}py_modem_fck@a00ti,omap3-interface-clock} y _sad2d_ick@a10ti,omap3-interface-clock}@y _mad2d_ick@a18ti,omap3-interface-clock}@y _mspro_fck@a00ti,wait-gate-clock}y ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock}!y _qssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock}!y @$_rssi_ssr_fck_3430es2ti,composite-clock}qr_sssi_sst_fck_3430es2fixed-factor-clock}s'_hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Ky _ssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}ty _usim_gate_fck@c00ti,composite-gate-clock}G y _sys_d2_ckfixed-factor-clock} '_vomap_96m_d2_fckfixed-factor-clock}G'_womap_96m_d4_fckfixed-factor-clock}G'_xomap_96m_d8_fckfixed-factor-clock}G'_yomap_96m_d10_fckfixed-factor-clock}G' _zdpll5_m2_d4_ckfixed-factor-clock}u'_{dpll5_m2_d8_ckfixed-factor-clock}u'_|dpll5_m2_d16_ckfixed-factor-clock}u'_}dpll5_m2_d20_ckfixed-factor-clock}u'_~usim_mux_fck@c40ti,composite-mux-clock(} vwxyz{|}~y @_usim_fckti,composite-clock}usim_ick@c10ti,omap3-interface-clock}Py  _dpll5_ck@d04ti,omap3-dpll-clock} y  $ L 4_dpll5_m2_ck@d50ti,divider-clock}y P_usgx_gate_fck@b00ti,composite-gate-clock}(y _core_d3_ckfixed-factor-clock}('_core_d4_ckfixed-factor-clock}('_core_d6_ckfixed-factor-clock}('_omap_192m_alwon_fckfixed-factor-clock}$'_core_d2_ckfixed-factor-clock}('_sgx_mux_fck@b40ti,composite-mux-clock },y @_sgx_fckti,composite-clock}sgx_ick@b10ti,wait-gate-clock}@y _cpefuse_fck@a08ti,gate-clock} y _ts_fck@a08ti,gate-clock}By _usbtll_fck@a08ti,wait-gate-clock}uy _usbtll_ick@a18ti,omap3-interface-clock}Ly _mmchs3_ick@a10ti,omap3-interface-clock}Ly _mmchs3_fck@a00ti,wait-gate-clock}y _dss1_alwon_fck_3430es2@e00ti,dss-gate-clock}yb_dss_ick_3430es2@e10ti,omap3-dss-interface-clock}Ay_usbhost_120m_fck@1400ti,gate-clock}uy_usbhost_48m_fck@1400ti,dss-gate-clock}2y_usbhost_ick@1410ti,omap3-dss-interface-clock}Ay_clockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}hdpll4_clkdmti,clockdomain}wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}od2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }counter@48320000ti,omap-counter32kyH2  counter_32kinterrupt-controller@48200000ti,omap3-intcyH _dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmayH`  `dma_gpio@48310000ti,omap3-gpioyH1gpio1 _ gpio@49050000ti,omap3-gpioyIgpio2 en_usb2_port!'2enable usb2 portgpio@49052000ti,omap3-gpioyI gpio3 gpio@49054000ti,omap3-gpioyI@ gpio4 gpio@49056000ti,omap3-gpioyI`!gpio5 _gpio@49058000ti,omap3-gpioyI"gpio6 _serial@4806a000ti,omap3-uartyH <HR12txrxuart1lserial@4806c000ti,omap3-uartyH<IJ34txrxuart2lserial@49020000ti,omap3-uartyI<Jn56txrxuart3lGdefaultUi2c@48070000 ti,omap3-i2cyH8txrx+i2c1'@twl@48yH  ti,twl4030GdefaultUrtcti,twl4030-rtc bciti,twl4030-bci P^ jvacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2usb_1v8w@w@{regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' _regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0_regulator-vmmc2ti,twl4030-vmmc2:0_regulator-vusb1v5ti,twl4030-vusb1v5_regulator-vusb1v8ti,twl4030-vusb1v8_regulator-vusb3v1ti,twl4030-vusb3v1_regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@{_regulator-vsimti,twl4030-vsimw@-_gpioti,twl4030-gpio _en_on_board_gpio_61!'2en_hsusb2_clktwl4030-usbti,twl4030-usb _pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad8  7 Smadcti,twl4030-madc_power1ti,twl4030-power-omap3-evmti,twl4030-power-idle&i2c@48072000 ti,omap3-i2cyH 9txrx+i2c2i2c@48060000 ti,omap3-i2cyH=txrx+i2c3tvp5146@5c ti,tvp5146m2y\mailbox@48094000ti,omap3-mailboxmailboxyH @6BTdsp f qspi@48098000ti,omap2-mcspiyH A+mcspi1|@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3tsc2046@0y ti,tsc2046B@@(  spi@4809a000ti,omap2-mcspiyH B+mcspi2| +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [+mcspi3| tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiyH 0+mcspi4|FGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-hsmmcyH Smmc1=>txrx<S+7DGdefaultUmmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrx+ND\+GdefaultUwlcore@2 ti,wl1271y oImmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuyH mmu_isp_mmu@5d000000ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< commontxrxmcbsp1 txrx}fck disabledmcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrx}fckick disabledmcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrx}fckick disabledmcbsp@49026000ti,omap3-mcbspyI`mpu 67 commontxrxmcbsp4txrx}fck disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR commontxrxmcbsp5txrx}fck disabledsham@480c3000ti,omap3-shamshamyH 0d1Erxtimer@48318000ti,omap3430-timeryH1%timer1timer@49032000ti,omap3430-timeryI &timer2timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5timer@4903a000ti,omap3430-timeryI*timer6timer@4903c000ti,omap3430-timeryI+timer7timer@4903e000ti,omap3430-timeryI,timer8timer@49040000ti,omap3430-timeryI-timer9timer@48086000ti,omap3430-timeryH`.timer10timer@48088000ti,omap3430-timeryH/timer11timer@48304000ti,omap3430-timeryH0@_timer12 usbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs+ ehci-phyohci@48064400ti,ohci-omap3yHDL%ehci@48064800 ti,ehci-omapyHHM=gpmc@6e000000ti,omap3430-gpmcgpmcynrxtxBN+  0,_ethernet@gpmcsmsc,lan9221smsc,lan9115`k}(-&5-CRctxKK'7ER  yGdefaultUnand@0,0ti,omap2-nand y hmicron,mt29f2g16abdhcwkbch8,,",C(&6t@RRcR(+usb_otg_hs@480ab000ti,omap3-musbyH \]mcdma usb_otg_hs = usb2-phy2dss@48050000 ti,omap3-dssyHok dss_core}fck+GdefaultUdispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H protophypll disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  disabled dss_venc}fckportendpoint  _ssi-controller@48058000 ti,omap3-ssissiokyHHsysgddGgdd_mpu+ }s ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHHtxrxCDssi-port@4805b000ti,omap3-ssi-portyHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$+ *GdefaultUpinmux_ehci_phy_pinsg_pinmux_hsusb2_2_pins0g   " _isp@480bc000 ti,omap3-ispyH H | '{l .ports+bandgap@48002524yH%$ti,omap34xx-bandgap :_ target-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreyH $sysc P} fck+ H smartreflex@0ti,omap3-smartreflex-coreytarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivayH $sysc P} fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivaythermal-zonescpu_thermal ] s N   regulator-vddvarioregulator-fixed vddvario{_regulator-vdd33aregulator-fixedvdd33a{_hsusb2_power_regregulator-fixed hsusb2_vbus2Z2Z    p _ hsusb2_phyusb-nop-xceiv   GdefaultU_leds gpio-ledsledb omap3evm::ledb ! default-onwl12xx_vmmcregulator-fixedvwl1271w@w@   p  GdefaultU_backlightgpio-backlight  !regulator-lcd-3v3regulator-fixedlcd_3v32Z2Z p  _displaysharp,ls037v7dw01 lcd    $ '  portendpoint _memory@80000000mmemoryy compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsgpio-hoggpiosoutput-lowline-nameinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsti,use_poweroff#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xywakeup-sourcependown-gpioti,dual-voltpbias-supplyvmmc-supplyvqmmc-supplybus-widthnon-removablecap-power-off-cardref-clock-frequencystatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addresslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-psmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowervdds_dsi-supplyvdda_video-supplyremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsti,sysc-maskpolling-delay-passivepolling-delaycoefficientsthermal-sensorsstartup-delay-usenable-active-highreset-gpioslabellinux,default-triggervin-supplydefault-onpower-supplyenvdd-supplyenable-gpiosmode-gpios