y8( Egumstix,omap3-overo-tobiduogumstix,omap3-overoti,omap36xxti,omap3 +07OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuochosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8lcpux|cpus 'O 57pmu@54000000arm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busxh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busx + pinmux@30 ti,omap3-padconfpinctrl-singlex08+:defaultHRpinmux_uart2_pins Z<>@BRpinmux_i2c1_pinsZRpinmux_mmc1_pins0ZRpinmux_mmc2_pins0Z(*,.02Rpinmux_w3cbw003c_pinsZlRpinmux_hsusb2_pins@Z      Rpinmux_twl4030_pinsZARpinmux_i2c3_pinsZRpinmux_uart3_pinsZnpRscm_conf@270sysconsimple-busxp0+ p0Rpbias_regulator@2b0ti,pbias-omap3ti,pbias-omapxnpbias_mmc_omap2430upbias_mmc_omap2430w@-Rclocks+mcbsp5_mux_fck@68ti,composite-mux-clock|xhRmcbsp5_fckti,composite-clock|Rmcbsp1_mux_fck@4ti,composite-mux-clock|xR mcbsp1_fckti,composite-clock| Rmcbsp2_mux_fck@4ti,composite-mux-clock| xR mcbsp2_fckti,composite-clock| Rmcbsp3_mux_fck@68ti,composite-mux-clock| xhRmcbsp3_fckti,composite-clock|Rmcbsp4_mux_fck@68ti,composite-mux-clock| xhRmcbsp4_fckti,composite-clock|Rclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlex \+pinmux_twl4030_vpins ZRaes@480c5000 ti,omap3-aesaesxH PPABtxrxprm@48306000 ti,omap3-prmxH0`@ clocks+virt_16_8m_ck fixed-clockYRosc_sys_ck@d40 ti,mux-clock|x @Rsys_ck@1270ti,divider-clock|xpRsys_clkout1@d70ti,gate-clock|x pdpll3_x2_ckfixed-factor-clock|dpll3_m2x2_ckfixed-factor-clock|Rdpll4_x2_ckfixed-factor-clock|corex2_fckfixed-factor-clock|Rwkup_l4_ickfixed-factor-clock|RNcorex2_d3_fckfixed-factor-clock|Rcorex2_d5_fckfixed-factor-clock|Rclockdomainscm@48004000 ti,omap3-cmxH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockR@virt_12m_ck fixed-clockRvirt_13m_ck fixed-clock]@Rvirt_19200000_ck fixed-clock$Rvirt_26000000_ck fixed-clockRvirt_38_4m_ck fixed-clockIRdpll4_ck@d00ti,omap3-dpll-per-j-type-clock|x D 0Rdpll4_m2_ck@d48ti,divider-clock|?x HR dpll4_m2x2_mul_ckfixed-factor-clock| R!dpll4_m2x2_ck@d00ti,hsdiv-gate-clock|!x $R"omap_96m_alwon_fckfixed-factor-clock|"R)dpll3_ck@d00ti,omap3-dpll-core-clock|x @ 0Rdpll3_m3_ck@1140ti,divider-clock|x@R#dpll3_m3x2_mul_ckfixed-factor-clock|#R$dpll3_m3x2_ck@d00ti,hsdiv-gate-clock|$ x $R%emu_core_alwon_ckfixed-factor-clock|%Rbsys_altclk fixed-clockR.mcbsp_clks fixed-clockRdpll3_m2_ck@d40ti,divider-clock|x @Rcore_ckfixed-factor-clock|R&dpll1_fck@940ti,divider-clock|&x @R'dpll1_ck@904ti,omap3-dpll-clock|'x  $ @ 4Rdpll1_x2_ckfixed-factor-clock|R(dpll1_x2m2_ck@944ti,divider-clock|(x DR<cm_96m_fckfixed-factor-clock|)R*omap_96m_fck@d40 ti,mux-clock|*x @REdpll4_m3_ck@e40ti,divider-clock| x@R+dpll4_m3x2_mul_ckfixed-factor-clock|+R,dpll4_m3x2_ck@d00ti,hsdiv-gate-clock|,x $R-omap_54m_fck@d40 ti,mux-clock|-.x @R8cm_96m_d2_fckfixed-factor-clock|*R/omap_48m_fck@d40 ti,mux-clock|/.x @R0omap_12m_fckfixed-factor-clock|0RGdpll4_m4_ck@e40ti,divider-clock| x@R1dpll4_m4x2_mul_ckti,fixed-factor-clock|1:HUR2dpll4_m4x2_ck@d00ti,gate-clock|2x $URdpll4_m5_ck@f40ti,divider-clock|?x@R3dpll4_m5x2_mul_ckti,fixed-factor-clock|3:HUR4dpll4_m5x2_ck@d00ti,hsdiv-gate-clock|4x $URjdpll4_m6_ck@1140ti,divider-clock|?x@R5dpll4_m6x2_mul_ckfixed-factor-clock|5R6dpll4_m6x2_ck@d00ti,hsdiv-gate-clock|6x $R7emu_per_alwon_ckfixed-factor-clock|7Rcclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock|&x pR9clkout2_src_mux_ck@d70ti,composite-mux-clock|&*8x pR:clkout2_src_ckti,composite-clock|9:R;sys_clkout2@d70ti,divider-clock|;@x phmpu_ckfixed-factor-clock|<R=arm_fck@924ti,divider-clock|=x $emu_mpu_alwon_ckfixed-factor-clock|=Rdl3_ick@a40ti,divider-clock|&x @R>l4_ick@a40ti,divider-clock|>x @R?rm_ick@c40ti,divider-clock|?x @gpt10_gate_fck@a00ti,composite-gate-clock| x RAgpt10_mux_fck@a40ti,composite-mux-clock|@x @RBgpt10_fckti,composite-clock|ABgpt11_gate_fck@a00ti,composite-gate-clock| x RCgpt11_mux_fck@a40ti,composite-mux-clock|@x @RDgpt11_fckti,composite-clock|CDcore_96m_fckfixed-factor-clock|ERmmchs2_fck@a00ti,wait-gate-clock|x Rmmchs1_fck@a00ti,wait-gate-clock|x Ri2c3_fck@a00ti,wait-gate-clock|x Ri2c2_fck@a00ti,wait-gate-clock|x Ri2c1_fck@a00ti,wait-gate-clock|x Rmcbsp5_gate_fck@a00ti,composite-gate-clock| x Rmcbsp1_gate_fck@a00ti,composite-gate-clock| x R core_48m_fckfixed-factor-clock|0RFmcspi4_fck@a00ti,wait-gate-clock|Fx Rmcspi3_fck@a00ti,wait-gate-clock|Fx Rmcspi2_fck@a00ti,wait-gate-clock|Fx Rmcspi1_fck@a00ti,wait-gate-clock|Fx Ruart2_fck@a00ti,wait-gate-clock|Fx Ruart1_fck@a00ti,wait-gate-clock|Fx  Rcore_12m_fckfixed-factor-clock|GRHhdq_fck@a00ti,wait-gate-clock|Hx Rcore_l3_ickfixed-factor-clock|>RIsdrc_ick@a10ti,wait-gate-clock|Ix Rgpmc_fckfixed-factor-clock|Icore_l4_ickfixed-factor-clock|?RJmmchs2_ick@a10ti,omap3-interface-clock|Jx Rmmchs1_ick@a10ti,omap3-interface-clock|Jx Rhdq_ick@a10ti,omap3-interface-clock|Jx Rmcspi4_ick@a10ti,omap3-interface-clock|Jx Rmcspi3_ick@a10ti,omap3-interface-clock|Jx Rmcspi2_ick@a10ti,omap3-interface-clock|Jx Rmcspi1_ick@a10ti,omap3-interface-clock|Jx Ri2c3_ick@a10ti,omap3-interface-clock|Jx Ri2c2_ick@a10ti,omap3-interface-clock|Jx Ri2c1_ick@a10ti,omap3-interface-clock|Jx Ruart2_ick@a10ti,omap3-interface-clock|Jx Ruart1_ick@a10ti,omap3-interface-clock|Jx  Rgpt11_ick@a10ti,omap3-interface-clock|Jx  Rgpt10_ick@a10ti,omap3-interface-clock|Jx  Rmcbsp5_ick@a10ti,omap3-interface-clock|Jx  Rmcbsp1_ick@a10ti,omap3-interface-clock|Jx  Romapctrl_ick@a10ti,omap3-interface-clock|Jx Rdss_tv_fck@e00ti,gate-clock|8xRdss_96m_fck@e00ti,gate-clock|ExRdss2_alwon_fck@e00ti,gate-clock|xRdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock|x RKgpt1_mux_fck@c40ti,composite-mux-clock|@x @RLgpt1_fckti,composite-clock|KLaes2_ick@a10ti,omap3-interface-clock|Jx Rwkup_32k_fckfixed-factor-clock|@RMgpio1_dbck@c00ti,gate-clock|Mx Rsha12_ick@a10ti,omap3-interface-clock|Jx Rwdt2_fck@c00ti,wait-gate-clock|Mx Rwdt2_ick@c10ti,omap3-interface-clock|Nx Rwdt1_ick@c10ti,omap3-interface-clock|Nx Rgpio1_ick@c10ti,omap3-interface-clock|Nx Romap_32ksync_ick@c10ti,omap3-interface-clock|Nx Rgpt12_ick@c10ti,omap3-interface-clock|Nx Rgpt1_ick@c10ti,omap3-interface-clock|Nx Rper_96m_fckfixed-factor-clock|)R per_48m_fckfixed-factor-clock|0ROuart3_fck@1000ti,wait-gate-clock|Ox Rgpt2_gate_fck@1000ti,composite-gate-clock|xRPgpt2_mux_fck@1040ti,composite-mux-clock|@x@RQgpt2_fckti,composite-clock|PQgpt3_gate_fck@1000ti,composite-gate-clock|xRRgpt3_mux_fck@1040ti,composite-mux-clock|@x@RSgpt3_fckti,composite-clock|RSgpt4_gate_fck@1000ti,composite-gate-clock|xRTgpt4_mux_fck@1040ti,composite-mux-clock|@x@RUgpt4_fckti,composite-clock|TUgpt5_gate_fck@1000ti,composite-gate-clock|xRVgpt5_mux_fck@1040ti,composite-mux-clock|@x@RWgpt5_fckti,composite-clock|VWgpt6_gate_fck@1000ti,composite-gate-clock|xRXgpt6_mux_fck@1040ti,composite-mux-clock|@x@RYgpt6_fckti,composite-clock|XYgpt7_gate_fck@1000ti,composite-gate-clock|xRZgpt7_mux_fck@1040ti,composite-mux-clock|@x@R[gpt7_fckti,composite-clock|Z[gpt8_gate_fck@1000ti,composite-gate-clock| xR\gpt8_mux_fck@1040ti,composite-mux-clock|@x@R]gpt8_fckti,composite-clock|\]gpt9_gate_fck@1000ti,composite-gate-clock| xR^gpt9_mux_fck@1040ti,composite-mux-clock|@x@R_gpt9_fckti,composite-clock|^_per_32k_alwon_fckfixed-factor-clock|@R`gpio6_dbck@1000ti,gate-clock|`xRgpio5_dbck@1000ti,gate-clock|`xRgpio4_dbck@1000ti,gate-clock|`xRgpio3_dbck@1000ti,gate-clock|`xRgpio2_dbck@1000ti,gate-clock|`x Rwdt3_fck@1000ti,wait-gate-clock|`x Rper_l4_ickfixed-factor-clock|?Ragpio6_ick@1010ti,omap3-interface-clock|axRgpio5_ick@1010ti,omap3-interface-clock|axRgpio4_ick@1010ti,omap3-interface-clock|axRgpio3_ick@1010ti,omap3-interface-clock|axRgpio2_ick@1010ti,omap3-interface-clock|ax Rwdt3_ick@1010ti,omap3-interface-clock|ax Ruart3_ick@1010ti,omap3-interface-clock|ax Ruart4_ick@1010ti,omap3-interface-clock|axRgpt9_ick@1010ti,omap3-interface-clock|ax Rgpt8_ick@1010ti,omap3-interface-clock|ax Rgpt7_ick@1010ti,omap3-interface-clock|axRgpt6_ick@1010ti,omap3-interface-clock|axRgpt5_ick@1010ti,omap3-interface-clock|axRgpt4_ick@1010ti,omap3-interface-clock|axRgpt3_ick@1010ti,omap3-interface-clock|axRgpt2_ick@1010ti,omap3-interface-clock|axRmcbsp2_ick@1010ti,omap3-interface-clock|axRmcbsp3_ick@1010ti,omap3-interface-clock|axRmcbsp4_ick@1010ti,omap3-interface-clock|axRmcbsp2_gate_fck@1000ti,composite-gate-clock|xR mcbsp3_gate_fck@1000ti,composite-gate-clock|xRmcbsp4_gate_fck@1000ti,composite-gate-clock|xRemu_src_mux_ck@1140 ti,mux-clock|bcdx@Reemu_src_ckti,clkdm-gate-clock|eRfpclk_fck@1140ti,divider-clock|fx@pclkx2_fck@1140ti,divider-clock|fx@atclk_fck@1140ti,divider-clock|fx@traceclk_src_fck@1140 ti,mux-clock|bcdx@Rgtraceclk_fck@1140ti,divider-clock|g x@secure_32k_fck fixed-clockRhgpt12_fckfixed-factor-clock|hwdt1_fckfixed-factor-clock|hsecurity_l4_ick2fixed-factor-clock|?Riaes1_ick@a14ti,omap3-interface-clock|ix rng_ick@a14ti,omap3-interface-clock|ix sha11_ick@a14ti,omap3-interface-clock|ix des1_ick@a14ti,omap3-interface-clock|ix cam_mclk@f00ti,gate-clock|jxUcam_ick@f10!ti,omap3-no-wait-interface-clock|?xRcsi2_96m_fck@f00ti,gate-clock|xRsecurity_l3_ickfixed-factor-clock|>Rkpka_ick@a14ti,omap3-interface-clock|kx icr_ick@a10ti,omap3-interface-clock|Jx des2_ick@a10ti,omap3-interface-clock|Jx mspro_ick@a10ti,omap3-interface-clock|Jx mailboxes_ick@a10ti,omap3-interface-clock|Jx ssi_l4_ickfixed-factor-clock|?Rrsr1_fck@c00ti,wait-gate-clock|x Rsr2_fck@c00ti,wait-gate-clock|x Rsr_l4_ickfixed-factor-clock|?dpll2_fck@40ti,divider-clock|&x@Rldpll2_ck@4ti,omap3-dpll-clock|lx$@4~Rmdpll2_m2_ck@44ti,divider-clock|mxDRniva2_ck@0ti,wait-gate-clock|nxRmodem_fck@a00ti,omap3-interface-clock|x Rsad2d_ick@a10ti,omap3-interface-clock|>x Rmad2d_ick@a18ti,omap3-interface-clock|>x Rmspro_fck@a00ti,wait-gate-clock|x ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock|x Rossi_ssr_div_fck_3430es2@a40ti,composite-divider-clock|x @$Rpssi_ssr_fck_3430es2ti,composite-clock|opRqssi_sst_fck_3430es2fixed-factor-clock|qRhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock|Ix Rssi_ick_3430es2@a10ti,omap3-ssi-interface-clock|rx Rusim_gate_fck@c00ti,composite-gate-clock|E x R}sys_d2_ckfixed-factor-clock|Rtomap_96m_d2_fckfixed-factor-clock|ERuomap_96m_d4_fckfixed-factor-clock|ERvomap_96m_d8_fckfixed-factor-clock|ERwomap_96m_d10_fckfixed-factor-clock|E Rxdpll5_m2_d4_ckfixed-factor-clock|sRydpll5_m2_d8_ckfixed-factor-clock|sRzdpll5_m2_d16_ckfixed-factor-clock|sR{dpll5_m2_d20_ckfixed-factor-clock|sR|usim_mux_fck@c40ti,composite-mux-clock(|tuvwxyz{|x @R~usim_fckti,composite-clock|}~usim_ick@c10ti,omap3-interface-clock|Nx  Rdpll5_ck@d04ti,omap3-dpll-clock|x  $ L 4~Rdpll5_m2_ck@d50ti,divider-clock|x PRssgx_gate_fck@b00ti,composite-gate-clock|&x Rcore_d3_ckfixed-factor-clock|&Rcore_d4_ckfixed-factor-clock|&Rcore_d6_ckfixed-factor-clock|&Romap_192m_alwon_fckfixed-factor-clock|"Rcore_d2_ckfixed-factor-clock|&Rsgx_mux_fck@b40ti,composite-mux-clock |*x @Rsgx_fckti,composite-clock|sgx_ick@b10ti,wait-gate-clock|>x Rcpefuse_fck@a08ti,gate-clock|x Rts_fck@a08ti,gate-clock|@x Rusbtll_fck@a08ti,wait-gate-clock|sx Rusbtll_ick@a18ti,omap3-interface-clock|Jx Rmmchs3_ick@a10ti,omap3-interface-clock|Jx Rmmchs3_fck@a00ti,wait-gate-clock|x Rdss1_alwon_fck_3430es2@e00ti,dss-gate-clock|xURdss_ick_3430es2@e10ti,omap3-dss-interface-clock|?xRusbhost_120m_fck@1400ti,gate-clock|sxRusbhost_48m_fck@1400ti,dss-gate-clock|0xRusbhost_ick@1410ti,omap3-dss-interface-clock|?xRuart4_fck@1000ti,wait-gate-clock|OxRclockdomainscore_l3_clkdmti,clockdomain|dpll3_clkdmti,clockdomain|dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainl|emu_clkdmti,clockdomain|fdpll4_clkdmti,clockdomain|wkup_clkdmti,clockdomain$|dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|cam_clkdmti,clockdomain|iva2_clkdmti,clockdomain|dpll2_clkdmti,clockdomain|md2d_clkdmti,clockdomain |dpll5_clkdmti,clockdomain|sgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |counter@48320000ti,omap-counter32kxH2  counter_32kinterrupt-controller@48200000ti,omap3-intcxH Rdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaxH`  `dmaRgpio@48310000ti,omap3-gpioxH1gpio1Rgpio@49050000ti,omap3-gpioxIgpio2R gpio@49052000ti,omap3-gpioxI gpio3Rgpio@49054000ti,omap3-gpioxI@ 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regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0Rregulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5Rregulator-vusb1v8ti,twl4030-vusb1v8Rregulator-vusb3v1ti,twl4030-vusb3v1Rregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpioJtwl4030-usbti,twl4030-usb VdrRpwmti,twl4030-pwmpwmledti,twl4030-pwmledR pwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madcRi2c@48072000 ti,omap3-i2cxH 9txrx+i2c2 disabledi2c@48060000 ti,omap3-i2cxH=txrx+i2c3:defaultHeeprom@51 atmel,24c01xQlis33de@1dst,lis33dest,lis3lv02dx!3 E W iwxx &&* disabledmailbox@48094000ti,omap3-mailboxmailboxxH @9EWdsp i tspi@48098000ti,omap2-mcspixH A+mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspixH B+mcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspixH [+mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspixH 0+mcspi4FGtx0rx01w@480b2000 ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc1=>txrx:defaultHmmc@480b4000ti,omap3-hsmmcxH @Vmmc2/0txrx:defaultHmmc@480ad000ti,omap3-hsmmcxH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuxH mmu_ispRmmu@5d000000ti,omap2-iommux]mmu_iva disabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@mpu ;<  commontxrxmcbsp1 txrx|fck disabledmcbsp@49022000ti,omap3-mcbspxI I mpusidetone>? commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrx|fckickokayR mcbsp@49024000ti,omap3-mcbspxI@I mpusidetoneYZ commontxrxsidetonemcbsp3mcbsp3_sidetonetxrx|fckick disabledmcbsp@49026000ti,omap3-mcbspxI`mpu 67  commontxrxmcbsp4txrx|fck+ disabledmcbsp@48096000ti,omap3-mcbspxH `mpu QR  commontxrxmcbsp5txrx|fck disabledsham@480c3000ti,omap3-shamshamxH 0d1Erxtimer@48318000ti,omap3430-timerxH1%timer1<timer@49032000ti,omap3430-timerxI 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|fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivaxthermal-zonescpu_thermal   N   memory@0lmemoryxpwmleds pwm-ledsoveroovero:blue:COM  w5  mmc0soundti,omap-twl4030 #overo , hsusb2_power_regregulator-fixed uhsusb2_vbusLK@LK@ 5 :p KR hsusb2_phyusb-nop-xceiv ^ j Rregulator-w3cbw003c-npoweronregulator-fixeduregulator-w3cbw003c-npoweron2Z2Z 5  KRregulator-w3cbw003c-wifi-nreset:defaultHregulator-fixed uregulator-w3cbw003c-wifi-nreset2Z2Z 5 :'Rlis33-3v3-regregulator-fixedulis33-3v3-reg2Z2ZRlis33-1v8-regregulator-fixedulis33-1v8-regw@w@Rregulator-vddvarioregulator-fixed uvddvario uRregulator-vdd33aregulator-fixeduvdd33a uR compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-z#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplycap-sdio-irqnon-removable#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsti,sysc-maskti,sysc-sidlepolling-delay-passivepolling-delaycoefficientsthermal-sensorspwmsmax-brightnesslinux,default-triggerti,modelti,mcbspgpiostartup-delay-usenable-active-highreset-gpiosvcc-supplyregulator-always-on