8l(4'rockchip,rk3288-fennecrockchip,rk3288&7Rockchip RK3288 Fennec Boardaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5< Hcpu@501cpuarm,cortex-a12'@5Hcpu@502cpuarm,cortex-a12'@5Hcpu@503cpuarm,cortex-a12'@5Hcpu-opp-tableoperating-points-v2PHopp-126000000[b opp-216000000[ b opp-312000000[b opp-408000000[Qb opp-600000000[#Fb opp-696000000[)|b~opp-816000000[0,bB@opp-1008000000[<bopp-1200000000[Gbopp-1416000000[TfrbOopp-1512000000[ZJb opp-1608000000[_"bpamba simple-buspdma-controller@ff250000arm,pl330arm,primecell%@w5 apb_pclkHdma-controller@ff600000arm,pl330arm,primecell`@w5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@w5 apb_pclkHRreserved-memorypdma-unusable@fe000000oscillator fixed-clockn6xin24mH timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshc р 5Drvbiuciuciu-driveciu-sample  @#reset disableddwmmc@ff0d0000rockchip,rk3288-dw-mshc р 5Eswbiuciuciu-driveciu-sample ! @#reset disableddwmmc@ff0e0000rockchip,rk3288-dw-mshc р 5Ftxbiuciuciu-driveciu-sample "@#reset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshc р 5Guybiuciuciu-driveciu-sample #@#resetokay/9KVddefaultr saradc@ff100000rockchip,saradc $|5I[saradcapb_pclkW #saradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclk  txrx ,ddefaultr disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclk txrx -ddefaultr disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclktxrx .ddefaultr disabledi2c@ff140000rockchip,rk3288-i2c >i2c5Mddefaultr disabledi2c@ff150000rockchip,rk3288-i2c ?i2c5Oddefaultr disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pddefaultr  disabledi2c@ff170000rockchip,rk3288-i2c Ai2c5Qddefaultr! disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 75MUbaudclkapb_pclkddefaultr" disabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 85NVbaudclkapb_pclkddefaultr# disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 95OWbaudclkapb_pclkddefaultr$okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :5PXbaudclkapb_pclkddefaultr% disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;5QYbaudclkapb_pclkddefaultr& disabledthermal-zonesreserve_thermal'cpu_thermald'tripscpu_alert0ppassiveH(cpu_alert1$passiveH)cpu_crit_ criticalcooling-mapsmap0( map1) gpu_thermald'tripsgpu_alert0ppassiveH*gpu_crit_ criticalcooling-mapsmap0* tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk #tsadc-apbdinitdefaultsleepr+,+'=s disabledH'ethernet@ff290000rockchip,rk3288-gmac)Tmacirqeth_wake_irqd-85fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB #stmmacethokayq.inputddefaultr/0123rgmii 'B@ 40usb@ff500000 generic-ehciP 5usbhost5 usbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otghost6  usb2-phyokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otgotg/>@@ 7  usb2-phyokayusb@ff5c0000 generic-ehci\ 5usbhostokayi2c@ff650000rockchip,rk3288-i2ce <i2c5Lddefaultr8okaypmic@1brockchip,rk808&9xin32krk808-clkout2ddefaultr:;Mn|<<<<<<======regulatorsDCDC_REG1$6 qNpfvdd_armH regulator-state-memuDCDC_REG2$6 PNfvdd_gpuHkregulator-state-memB@DCDC_REG3$fvcc_ddrregulator-state-memDCDC_REG4$62ZN2Zfvcc_ioH=regulator-state-mem2ZLDO_REG1$62ZN2Z fvccio_pmuregulator-state-mem2ZLDO_REG2$62ZN2Zfvcca_33regulator-state-memuLDO_REG3$6B@NB@fvdd_10regulator-state-memB@LDO_REG4$6w@Nw@fvcc_wlregulator-state-memw@LDO_REG5$6w@N2Z fvccio_sdregulator-state-mem2ZLDO_REG6$6B@NB@ fvdd10_lcdregulator-state-memB@LDO_REG7$6w@Nw@fvcc_18regulator-state-memw@LDO_REG8$6w@Nw@ fvcc18_lcdregulator-state-memw@SWITCH_REG1$fvcc_sdregulator-state-memSWITCH_REG2$fvcc_lanH3regulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c5Nddefaultr> disabledpwm@ff680000rockchip,rk3288-pwmhddefaultr?5^pwm disabledpwm@ff680010rockchip,rk3288-pwmhddefaultr@5^pwm disabledpwm@ff680020rockchip,rk3288-pwmh ddefaultrA5^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0ddefaultrB5^pwm disabledbus_intmem@ff700000 mmio-srampppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsHpower-controller!rockchip,rk3288-power-controllerqh HUpd_vio@9 5chgfdehilkj$CDEFGHIJKpd_hevc@11 5opLMpd_video@12 5Npd_gpu@13 5OPreboot-modesyscon-reboot-modeRBRB RB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvd-%Hqjk$2#gׄeрxhрxhHsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwH-edp-phyrockchip,rk3288-dp-phy5h24mG disabledHeio-domains"rockchip,rk3288-io-voltage-domain disabledusbphyrockchip,rk3288-usb-phyokayddefaultrQ R9usb-phy@320G 5]phyclkH7usb-phy@334G45^phyclkH5usb-phy@348GH5_phyclkH6watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p O disabledsound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdifa hclkmclk5TRtx 6ddefaultrSd- disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2sa 5RRtxrxi2s_hclki2s_clk5RddefaultrTr disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk #crypto-rstokayiommu@ff900800rockchip,iommu@ Tiep_mmu5 aclkiface disablediommu@ff914000rockchip,iommu @P Tisp_mmu5 aclkiface disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclkU ilm #coreaxiahbvop@ff930000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vopU def #axiahbdclkVokayportH endpoint@0WHhendpoint@1XHfendpoint@2YH`endpoint@3ZHciommu@ff930300rockchip,iommu  Tvopb_mmu5 aclkifaceU okayHVvop@ff940000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vopU  #axiahbdclk[okayportH endpoint@0\Hiendpoint@1]Hgendpoint@2^Haendpoint@3_Hdiommu@ff940300rockchip,iommu  Tvopl_mmu5 aclkifaceU okayH[mipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclkU d- disabledportsportendpoint@0`HYendpoint@1aH^lvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdsdlcdcrbU d- disabledportsport@0endpoint@0cHZendpoint@1dH_dp@ff970000rockchip,rk3288-dp@ b5icdppclke dpo#dpd- disabledportsport@0endpoint@0fHXendpoint@1gH]hdmi@ff980000rockchip,rk3288-dw-hdmiad- g5hmniahbisfrcecU okayportsportendpoint@0hHWendpoint@1iH\iommu@ff9a0800rockchip,iommu Tvpu_mmu5 aclkiface disablediommu@ff9c0440rockchip,iommu @@@ o Thevc_mmu5 aclkiface disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ Tjobmmugpu5jU okaykgpu-opp-tableoperating-points-v2Hjopp@100000000[b~opp@200000000[ b~opp@300000000[bB@opp@400000000[ׄbopp@500000000[ebOopp@600000000[#Fbqos@ffaa0000syscon HOqos@ffaa0080syscon HPqos@ffad0000syscon HDqos@ffad0100syscon HEqos@ffad0180syscon HFqos@ffad0400syscon HGqos@ffad0480syscon HHqos@ffad0500syscon HCqos@ffad0800syscon HIqos@ffad0880syscon HJqos@ffad0900syscon HKqos@ffae0000syscon HNqos@ffaf0000syscon HLqos@ffaf0080syscon HMinterrupt-controller@ffc01000 arm,gic-400@ @ `   Hefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrld-pgpio0@ff750000rockchip,gpio-banku Q5@&6H9gpio1@ff780000rockchip,gpio-bankx R5A&6gpio2@ff790000rockchip,gpio-banky S5B&6gpio3@ff7a0000rockchip,gpio-bankz T5C&6gpio4@ff7b0000rockchip,gpio-bank{ U5D&6H4gpio5@ff7c0000rockchip,gpio-bank| V5E&6gpio6@ff7d0000rockchip,gpio-bank} W5F&6gpio7@ff7e0000rockchip,gpio-bank~ X5G&6gpio8@ff7f0000rockchip,gpio-bank Y5H&6hdmihdmi-cec-c0Blhdmi-cec-c7Blhdmi-ddc Bllpcfg-pull-upPHmpcfg-pull-down]Hnpcfg-pull-nonelHlpcfg-pull-none-12maly Hosleepglobal-pwroffBlH;ddrio-pwroffBlddr0-retentionBmddr1-retentionBmedpedp-hpdB ni2c0i2c0-xfer BllH8i2c1i2c1-xfer BllHi2c2i2c2-xfer B l lH>i2c3i2c3-xfer BllHi2c4i2c4-xfer BllH i2c5i2c5-xfer BllH!i2s0i2s0-bus`BllllllHTlcdclcdc-ctl@BllllHbsdmmcsdmmc-clkBlsdmmc-cmdBmsdmmc-cdBmsdmmc-bus1Bmsdmmc-bus4@Bmmmmsdio0sdio0-bus1Bmsdio0-bus4@Bmmmmsdio0-cmdBmsdio0-clkBlsdio0-cdBmsdio0-wpBmsdio0-pwrBmsdio0-bkpwrBmsdio0-intBmsdio1sdio1-bus1Bmsdio1-bus4@Bmmmmsdio1-cdBmsdio1-wpBmsdio1-bkpwrBmsdio1-intBmsdio1-cmdBmsdio1-clkBlsdio1-pwrB memmcemmc-clkBlH emmc-cmdBmHemmc-pwrB mHemmc-bus1Bmemmc-bus4@Bmmmmemmc-bus8BmmmmmmmmHspi0spi0-clkB mHspi0-cs0B mHspi0-txBmHspi0-rxBmHspi0-cs1Bmspi1spi1-clkB mHspi1-cs0B mHspi1-rxBmHspi1-txBmHspi2spi2-cs1Bmspi2-clkBmHspi2-cs0BmHspi2-rxBmHspi2-txB mHuart0uart0-xfer BmlH"uart0-ctsBmuart0-rtsBluart1uart1-xfer Bm lH#uart1-ctsB muart1-rtsB luart2uart2-xfer BmlH$uart3uart3-xfer BmlH%uart3-ctsB muart3-rtsB luart4uart4-xfer BmlH&uart4-ctsB muart4-rtsB ltsadcotp-gpioB lH+otp-outB lH,pwm0pwm0-pinBlH?pwm1pwm1-pinBlH@pwm2pwm2-pinBlHApwm3pwm3-pinBlHBgmacrgmii-pinsBlllloooolll oollH/rmii-pinsBllllllllllphy-intB mH2phy-pmebBmH1phy-rstBpH0spdifspdif-txB lHSpcfg-output-highHppcfg-output-lowpcfg-pull-none-drv-8maypcfg-pull-up-drv-8maPypmicpmic-intBmH:usbphyhost-drvBlHQmemory@0memoryexternal-gmac-clock fixed-clocksY@ ext_gmacH.vsys-regulatorregulator-fixedfvcc_sys6LK@NLK@$H< #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclockscpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeeddisable-wpnon-removablepinctrl-namespinctrl-0#io-channel-cellsdmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsvbus_drv-gpios#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-low