m8 ( Mgoogle,veyron-mickey-rev8google,veyron-mickey-rev7google,veyron-mickey-rev6google,veyron-mickey-rev5google,veyron-mickey-rev4google,veyron-mickey-rev3google,veyron-mickey-rev2google,veyron-mickey-rev1google,veyron-mickey-rev0google,veyron-mickeygoogle,veyronrockchip,rk3288&7Google Mickeyaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5< Hcpu@501cpuarm,cortex-a12'@5Hcpu@502cpuarm,cortex-a12'@5Hcpu@503cpuarm,cortex-a12'@5Hcpu-opp-tableoperating-points-v2PHopp-126000000[b opp-216000000[ b opp-408000000[Qb opp-600000000[#Fb opp-696000000[)|b~opp-816000000[0,bB@opp-1008000000[<bopp-1200000000[Gbopp-1416000000[TfrbOopp-1512000000[ZJbopp-1608000000[_"b opp-1704000000[ebpopp-1800000000[kIb\amba simple-buspdma-controller@ff250000arm,pl330arm,primecell%@w5 apb_pclkHdma-controller@ff600000arm,pl330arm,primecell`@w5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@w5 apb_pclkHWreserved-memorypdma-unusable@fe000000oscillator fixed-clockn6xin24mH timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshc р 5Drvbiuciuciu-driveciu-sample  @#reset disableddwmmc@ff0d0000rockchip,rk3288-dw-mshc р 5Eswbiuciuciu-driveciu-sample ! @#resetokay/9JWm xdefault dwmmc@ff0e0000rockchip,rk3288-dw-mshc р 5Ftxbiuciuciu-driveciu-sample "@#reset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshc р 5Guybiuciuciu-driveciu-sample #@#resetokay/mxdefault saradc@ff100000rockchip,saradc $'5I[saradcapb_pclkW #saradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclk9  >txrx ,default disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclk9 >txrx -default disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclk9>txrx .default !"#okayH flash@0jedec,spi-nor[i2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault$okaym2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault% disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault& disabledm2,i2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault'okaym,Hmserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 75MUbaudclkapb_pclkdefault ()*okayMlserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 85NVbaudclkapb_pclkdefault+okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 95OWbaudclkapb_pclkdefault,okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :5PXbaudclkapb_pclkdefault- disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;5QYbaudclkapb_pclkdefault. disabledthermal-zonesreserve_thermal/cpu_thermald/tripscpu_crit$_0 criticalcpu_alert_almost_warm$0passivecpu_alert_warm$0passiveH0cpu_alert_almost_hot$80passiveH1cpu_alert_hot$@P0passiveH2cpu_alert_hotter$H 0passiveH3cpu_alert_very_hot$L0passiveH4cooling-mapscpu_warm_limit_cpu;0 @cpu_almost_hot_limit_cpu;1 @cpu_hot_limit_cpu;2 @cpu_hotter_limit_cpu;3 @cpu_very_hot_limit_cpu;4 @gpu_thermald/tripsgpu_alert0$p0passiveH5gpu_crit$_0 criticalcooling-mapsmap0;5 @tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk #tsadc-apbinitdefaultsleep6O7Y6cysokayH/ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq885fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB #stmmaceth disabledusb@ff500000 generic-ehciP 5usbhost9usb disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otghost: usb2-phy disabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otghost -@@ ; usb2-phyokayz<;usb@ff5c0000 generic-ehci\ 5usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5Ldefault<okaym2dpmic@1brockchip,rk808xin32kwifibt_32kin&=default >?@StAB BH|regulatorsDCDC_REG1vdd_arm# q; SqH regulator-state-memhDCDC_REG2vdd_gpu# 5;SqHqregulator-state-memB@DCDC_REG3 vcc135_ddrregulator-state-memDCDC_REG4vcc_18#w@;w@Hregulator-state-memw@LDO_REG3vdd_10#B@;B@regulator-state-memB@LDO_REG7 vdd10_lcd#B@;B@SWITCH_REG1 vcc33_lcdHVregulator-state-memhLDO_REG8#w@;w@ vcc18_lcdi2c@ff660000rockchip,rk3288-i2cf =i2c5NdefaultC disabledm2 pwm@ff680000rockchip,rk3288-pwmhdefaultD5^pwm disabledpwm@ff680010rockchip,rk3288-pwmhdefaultE5^pwmokaypwm@ff680020rockchip,rk3288-pwmh defaultF5^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0defaultG5^pwm disabledbus_intmem@ff700000 mmio-srampppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsHpower-controller!rockchip,rk3288-power-controllerh< HZpd_vio@9 5chgfdehilkj$HIJKLMNOPpd_hevc@11 5opQRpd_video@12 5Spd_gpu@13 5TUreboot-modesyscon-reboot-modeRB RBRB +RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv87Hjk$#gׄeрxhрxhHsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwH8edp-phyrockchip,rk3288-dp-phy5h24mD disabledHjio-domains"rockchip,rk3288-io-voltage-domainokayOAYdrAAVusbphyrockchip,rk3288-usb-phyokayusb-phy@320D 5]phyclkH;usb-phy@334D45^phyclkH9usb-phy@348DH5_phyclkH:watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif hclkmclk5T9W>tx 6defaultX8 disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 59WW>txrxi2s_hclki2s_clki2s_clk_out5RqdefaultYokaycypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk #crypto-rstokayiommu@ff900800rockchip,iommu@ iep_mmu5 aclkiface disablediommu@ff914000rockchip,iommu @P isp_mmu5 aclkiface disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclkZ ilm #coreaxiahbvop@ff930000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vopZ def #axiahbdclk$[okayportH endpoint@0+\Hnendpoint@1+]Hkendpoint@2+^Heendpoint@3+_Hhiommu@ff930300rockchip,iommu  vopb_mmu5 aclkifaceZ okayH[vop@ff940000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vopZ  #axiahbdclk$` disabledportH endpoint@0+aHoendpoint@1+bHlendpoint@2+cHfendpoint@3+dHiiommu@ff940300rockchip,iommu  vopl_mmu5 aclkifaceZ  disabledH`mipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclkZ 8 disabledportsportendpoint@0+eH^endpoint@1+fHclvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdslcdcgZ 8 disabledportsport@0endpoint@0+hH_endpoint@1+iHddp@ff970000rockchip,rk3288-dp@ b5icdppclkjdpo#dp8 disabledportsport@0endpoint@0+kH]endpoint@1+lHbhdmi@ff980000rockchip,rk3288-dw-hdmi8 g5hmniahbisfrcecZ okay;mportsportendpoint@0+nH\endpoint@1+oHaiommu@ff9a0800rockchip,iommu vpu_mmu5 aclkiface disablediommu@ff9c0440rockchip,iommu @@@ o hevc_mmu5 aclkiface disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu5pZ okayGqgpu-opp-tableoperating-points-v2Hpopp@100000000[b~opp@200000000[ b~opp@300000000[bB@opp@400000000[ׄbopp@500000000[ebOopp@600000000[#Fbqos@ffaa0000syscon HTqos@ffaa0080syscon HUqos@ffad0000syscon HIqos@ffad0100syscon HJqos@ffad0180syscon HKqos@ffad0400syscon HLqos@ffad0480syscon HMqos@ffad0500syscon HHqos@ffad0800syscon HNqos@ffad0880syscon HOqos@ffad0900syscon HPqos@ffae0000syscon HSqos@ffaf0000syscon HQqos@ffaf0080syscon HRinterrupt-controller@ffc01000 arm,gic-400Sh@ @ `   Hefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrl8pdefaultsleeprOrgpio0@ff750000rockchip,gpio-banku Q5@yShH=gpio1@ff780000rockchip,gpio-bankx R5AyShgpio2@ff790000rockchip,gpio-banky S5ByShH{gpio3@ff7a0000rockchip,gpio-bankz T5CyShgpio4@ff7b0000rockchip,gpio-bank{ U5DyShHgpio5@ff7c0000rockchip,gpio-bank| V5EyShgpio6@ff7d0000rockchip,gpio-bank} W5FyShgpio7@ff7e0000rockchip,gpio-bank~ X5GyShHBgpio8@ff7f0000rockchip,gpio-bank Y5HyShhdmihdmi-cec-c0shdmi-cec-c7shdmi-ddc sspower-hdmi-on sHpcfg-pull-upHtpcfg-pull-downHupcfg-pull-noneHspcfg-pull-none-12ma Hwsleepglobal-pwroffsHrddrio-pwroffsddr0-retentiontddr1-retentiontedpedp-hpd ui2c0i2c0-xfer ssH<i2c1i2c1-xfer ssH$i2c2i2c2-xfer  s sHCi2c3i2c3-xfer ssH%i2c4i2c4-xfer ssH&i2c5i2c5-xfer ssH'i2s0i2s0-bus`ssssssHYlcdclcdc-ctl@ssssHgsdmmcsdmmc-clkssdmmc-cmdtsdmmc-cdtsdmmc-bus1tsdmmc-bus4@ttttsdio0sdio0-bus1tsdio0-bus4@vvvvHsdio0-cmdvHsdio0-clkvHsdio0-cdtsdio0-wptsdio0-pwrtsdio0-bkpwrtsdio0-inttwifienable-hsH~bt-enable-lsH}sdio1sdio1-bus1tsdio1-bus4@ttttsdio1-cdtsdio1-wptsdio1-bkpwrtsdio1-inttsdio1-cmdtsdio1-clkssdio1-pwr temmcemmc-clkvHemmc-cmdvHemmc-pwr temmc-bus1temmc-bus4@ttttemmc-bus8vvvvvvvvHemmc-reset sHzspi0spi0-clk tHspi0-cs0 tHspi0-txtHspi0-rxtHspi0-cs1tspi1spi1-clk tHspi1-cs0 tHspi1-rxtHspi1-txtHspi2spi2-cs1tspi2-clktH spi2-cs0tH#spi2-rxtH"spi2-tx tH!uart0uart0-xfer tsH(uart0-ctstH)uart0-rtssH*uart1uart1-xfer t sH+uart1-cts tuart1-rts suart2uart2-xfer tsH,uart3uart3-xfer tsH-uart3-cts tuart3-rts suart4uart4-xfer tsH.uart4-cts tuart4-rts stsadcotp-gpio sH6otp-out sH7pwm0pwm0-pinsHDpwm1pwm1-pinsHEpwm2pwm2-pinsHFpwm3pwm3-pinsHGgmacrgmii-pinssssswwwwsss wwssrmii-pinsssssssssssspdifspdif-tx sHXpcfg-pull-none-drv-8maHvpcfg-pull-up-drv-8mapcfg-output-highpcfg-output-lowbuttonspwr-key-ltHxpmicpmic-int-ltH>dvs-1 uH?dvs-2uH@rebootap-warm-reset-h sHyrecovery-switchrec-mode-l ttpmtpm-int-hswrite-protectfw-wp-apsmemorymemorygpio-keys gpio-keysdefaultxpowerPower =t dtgpio-restart gpio-restart = defaulty emmc-pwrseqmmc-pwrseq-emmczdefault { Hsdio-pwrseqmmc-pwrseq-simple5| ext_clockdefault}~ H vcc-5vregulator-fixedvcc_5v#LK@;LK@ *Hvcc33-sysregulator-fixed vcc33_sys#2Z;2ZHvcc50-hdmiregulator-fixed vcc50_hdmi * 5 HB defaultvcc33_ioregulator-fixed vcc33_io *HA #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclockscpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsmax-frequencyfifo-depthreset-namesbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedrockchip,default-sample-phasedisable-wp#io-channel-cellsdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreg-shiftreg-io-widthassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphysphy-namesneeds-reset-on-resumedr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clock-parentsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc7-supplyvcc8-supplyvddio-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltregulator-suspend-mem-disabled#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cells#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpio