Ð þí.Ä8+(¬*à"amd,seattle-overdriveamd,seattle +37AMD Seattle (Rev.B0) Development Board (Overdrive)interrupt-controller@e1101000arm,gic-400arm,cortex-a15-gic=R+@cááð á á  g ráyv2m@e0080000arm,gic-v2m-frame�cytimerarm,armv8-timer0g ÿÿ ÿ ÿsmb simple-bus+r�clk100mhz_0 fixed-clock›¨õá¸adl3clk_100mhzclk375mhz fixed-clock›¨Z À¸ccpclk_375mhzclk333mhz fixed-clock›¨Ù-@¸sataclk_333mhzyclk500mhz_0 fixed-clock›¨Íe¸pcieclk_500mhzclk500mhz_1 fixed-clock›¨Íe¸dmaclk_500mhzclk250mhz_4 fixed-clock›¨æ²€¸miscclk_250mhzyclk100mhz_1 fixed-clock›¨õá¸uartspiclk_100mhzysata@e0300000snps,dwc-ahcicà0 gcË ÒÙsata@e0d00000 ædisabledsnps,dwc-ahcicàÐ gbËÒÙiommu@e0200000 arm,mmu-401cà ígLLÙyiommu@e0c00000 arm,mmu-401càÀígKKÙyi2c@e1000000æoksnps,designware-i2ccá geËi2c@e0050000æoksnps,designware-i2ccà gTËserial@e1010000arm,pl011arm,primecellcá gHË uartclkapb_pclkspi@e1020000æokarm,pl022arm,primecellcá gJË  apb_pclkspi@e1030000æokarm,pl022arm,primecellcá gIË  apb_pclk(+sdcard@0 mmc-spi-slotc/1-A € HP`p“gpio@e1040000 ædisabledarm,pl061arm,primecell§cá³ gg=RË  apb_pclkgpio@e1050000æokarm,pl061arm,primecell§cá³=R gfË  apb_pclkgpio@e0020000 ædisabledarm,pl061arm,primecell§cà³=R gnË  apb_pclkgpio@e0030000 ædisabledarm,pl061arm,primecell§cà³=R gmË  apb_pclkgpio@e0080000æokarm,pl061arm,primecell§cà³=R giË  apb_pclkccp@e0100000æokamd,ccp-seattle-v1acà gÙ Ò@BÃpcie@f0000000pci-host-ecam-generic+RÔpciàêcðõÿà !"#$%&'()*+Ù�CTrïÿ@@€æokiommu@e0a00000 arm,mmu-401cà ígMMÙyccn@e8000000 arm,ccn-504cè g|kcs@e0010000 ædisabled ipmi-kcsÔipmicà g… )clk250mhz_0 fixed-clock›¨æ²€¸xgmacclk0_dma_250mhzy clk250mhz_1 fixed-clock›¨æ²€¸xgmacclk0_ptp_250mhzy clk250mhz_2 fixed-clock›¨æ²€¸xgmacclk1_dma_250mhzy clk250mhz_3 fixed-clock›¨æ²€¸xgmacclk1_ptp_250mhzy xgmac@e0700000amd,xgbe-seattle-v1aPcàpàxá$á%`á%øHgEZ[\]C5O ] m �  ” ¦ ÀÚ¡¢£¤¥Ë  dma_clkptp_clkæxgmii Ò Ùxgmac@e0900000amd,xgbe-seattle-v1aPcà�à˜á$ á%€`á%üHgDUVWXB5O ] m �  ” ¦ ÀÚ±²³´µË  dma_clkptp_clkæxgmii ÒÙiommu@e0600000 arm,mmu-401cà`ígPPÙy iommu@e0800000 arm,mmu-401cà€ígOOÙycpus+cpu-mapcluster0core0ïcore1ïcluster1core0ïcore1ïcluster2core0ïcore1ïcluster3core0ïcore1ïcpu@0Ôcpuarm,cortex-a57cópsciÀ@ -€:@LYycpu@1Ôcpuarm,cortex-a57cópsciÀ@ -€:@LYycpu@100Ôcpuarm,cortex-a57cópsciÀ@ -€:@LYycpu@101Ôcpuarm,cortex-a57cópsciÀ@ -€:@LYycpu@200Ôcpuarm,cortex-a57cópsciÀ@ -€:@LYycpu@201Ôcpuarm,cortex-a57cópsciÀ@ -€:@LYycpu@300Ôcpuarm,cortex-a57cópsciÀ@ -€:@LYycpu@301Ôcpuarm,cortex-a57cópsciÀ@ -€:@LYyl2-cache0@"bpyl2-cache1@"bpyl2-cache2@"bpyl2-cache3@"bpyl3-cache�€@" bypmuarm,cortex-a57-pmu`g      �chosen /smb/serial@e1010000psci arm,psci-0.2úsmc compatibleinterrupt-parent#address-cells#size-cellsmodelinterrupt-controller#interrupt-cellsreginterruptsrangesphandlemsi-controllerdma-ranges#clock-cellsclock-frequencyclock-output-namesclocksiommusdma-coherentstatus#global-interrupts#iommu-cellsclock-namesspi-controllernum-csspi-max-frequencyvoltage-rangespl022,hierarchypl022,interfacepl022,com-modepl022,rx-level-trigpl022,tx-level-trig#gpio-cellsgpio-controlleramd,zlib-supportdevice_typebus-rangemsi-parentinterrupt-map-maskinterrupt-mapiommu-mapreg-sizereg-spacingamd,per-channel-interruptamd,speed-setamd,serdes-blwcamd,serdes-cdr-rateamd,serdes-pq-skewamd,serdes-tx-ampamd,serdes-dfe-tap-configamd,serdes-dfe-tap-enablemac-addressphy-modecpuenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsl2-cachecache-unifiednext-level-cachecache-levelinterrupt-affinitystdout-path