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cpu-debug@23010000&arm,coresight-cpu-debugarm,primecellR#±  Öapb_pclk  "etm@23040000"arm,coresight-etm4xarm,primecellR#±  Öapb_pclk  "m$out-portsportendpointì#m&cti@23020000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellR#±  Öapb_pclk $$ "funnel@230c0000+arm,coresight-dynamic-funnelarm,primecellR# ±  Öapb_pclk out-portsportendpointì%min-ports"1port@0Rendpointì&m#port@1Rendpointì'm+port@2Rendpointì(m.port@3Rendpointì)m1cpu-debug@23110000&arm,coresight-cpu-debugarm,primecellR#±  Öapb_pclk  *etm@23140000"arm,coresight-etm4xarm,primecellR#±  Öapb_pclk  *m,out-portsportendpointì+m'cti@23120000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellR#±  Öapb_pclk $, *cpu-debug@23210000&arm,coresight-cpu-debugarm,primecellR#!±  Öapb_pclk  -etm@23240000"arm,coresight-etm4xarm,primecellR#$±  Öapb_pclk  -m/out-portsportendpointì.m(cti@23220000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellR#"±  Öapb_pclk $/ -cpu-debug@23310000&arm,coresight-cpu-debugarm,primecellR#1±  Öapb_pclk  0etm@23340000"arm,coresight-etm4xarm,primecellR#4±  Öapb_pclk  0m2out-portsportendpointì1m)cti@23320000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellR#2±  Öapb_pclk $2 0cti@20020000 arm,coresight-ctiarm,primecellR ±  Öapb_pclk "1trig-conns@0R5F Xj$3trig-conns@1R5F Xj$4trig-conns@2R5FXj$5trig-conns@3RXj$6cti@20110000 arm,coresight-ctiarm,primecellR ±  Öapb_pclk "1trig-conns@0R5FXj }sys_profilertrig-conns@1RXj }watchdogtrig-conns@2RXj }g_countergpu@2d000000arm,juno-maliarm,mali-t624R-$h!"  �jobmmugpu±7 Ð adisabledsram@2e000000arm,juno-sram-nsmmio-sramR.€"1ÿ.€scp-sram@0arm,scmi-shmemR€mLscp-sram@80arm,scmi-shmemR€€mMscp-sram@100arm,scmi-shmemR€mNscp-sram@180arm,scmi-shmemR€€mOpcie@40000000<arm,juno-r1-pcieplda,xpressrich3-axipci-host-ecam-generic pciR@¬ÿ¶"1ÐTÿ_€€PPB@@8Ç€€€C�*ˆ‰Š‹Ò8 adisabledÝì9thermal-zonespmicöèd:socöèd:big-clusteröèd: adisabledlittle-clusteröèd: adisabledgpu0öèd: adisabledgpu1öèd: adisablediommu@7fb00000arm,mmu-401arm,smmu-v1R°h__¢¯Ðm;iommu@7fb10000arm,mmu-401arm,smmu-v1R±hcc¢¯m=iommu@7fb20000arm,mmu-401arm,smmu-v1R²haa¢¯m@iommu@7fb30000arm,mmu-401arm,smmu-v1R³hee¢¯ÐmEdma-controller@7ff00000arm,pl330arm,primecellRð*lhXYZ[\lmnoHü;;;;;;;;;±< Öapb_pclkhdlcd@7ff50000 arm,hdlcdRõ h]ü=±>Öpxlclkportendpointì?mDhdlcd@7ff60000 arm,hdlcdRö hUü@±>ÖpxlclkportendpointìAmCserial@7ff80000arm,pl011arm,primecellRø hS±B Öuartclkapb_pclki2c@7ffa0000snps,designware-i2cRú"1 hhJ€5ô± hdmi-transmitter@70 nxp,tda998xRpportendpointìCmAhdmi-transmitter@71 nxp,tda998xRqportendpointìDm?usb@7ffb0000 generic-ohciRû htüE±Fusb@7ffc0000 generic-ehciRü huüE±Fmemory-controller@7ffd0000arm,pl354arm,primecellRýhVW±  Öapb_pclkmemory@80000000 memory R€€€tlx-bus@60000000 simple-bus"1ÿ`*¨aliasesJ/serial@7ff80000chosenRserial0:115200n8psci arm,psci-0.2^smccpus"1cpu-mapcluster0core0 core1 cluster1core0 "core1 *core2 -core3 0idle-statesepscicpu-sleep-0arm,idle-stater‰š,«°»ÐmHcluster-sleep-0arm,idle-stater‰š�«°» ÄmIcpu@0arm,cortex-a57R cpuÌpsciÚÀç@ù€@%2G±7CHISfmcpu@1arm,cortex-a57R cpuÌpsciÚÀç@ù€@%2G±7CHISfmcpu@100arm,cortex-a53R cpuÌpsciÚ€ç@ù€@%€2J±7CHISBfŒm"cpu@101arm,cortex-a53R cpuÌpsciÚ€ç@ù€@%€2J±7CHISBfŒm*cpu@102arm,cortex-a53R cpuÌpsciÚ€ç@ù€@%€2J±7CHISBfŒm-cpu@103arm,cortex-a53R cpuÌpsciÚ€ç@ù€@%€2J±7CHISBfŒm0l2-cache0cacheÜ é@ûmGl2-cache1cacheÜé@ûmJpmu-a57arm,cortex-a57-pmuh€pmu-a53arm,cortex-a53-pmu0h€"*-0firmwarescmi arm,scmi“txrxžKK¥LM"1protocol@11R«m protocol@13R=“txrxžKK¥NOm7protocol@14R=m>protocol@15R¿m: modelcompatibleinterrupt-parent#address-cells#size-cells#clock-cellsclock-frequencyclock-output-namesphandleregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-ondebounce-intervalwakeup-sourcelinux,codelabelgpiosranges#interrupt-cellsinterrupt-map-maskinterrupt-maparm,hbiarm,vexpress,siteregbank-widthstatusinterruptsphy-modereg-io-widthsmsc,irq-active-highsmsc,irq-push-pullclocksvdd33a-supplyvddvario-supplyclock-namesassigned-clocksassigned-clock-parentsoffsetlinux,default-triggerdefault-statemax-frequencyvmmc-supplygpio-controller#gpio-cellsinterrupt-controllerframe-number#mbox-cellsmbox-name#iommu-cells#global-interruptspower-domainsdma-coherentmsi-controllerremote-endpointiommusarm,scatter-gatherreg-namescpuarm,cs-dev-assocarm,trig-in-sigsarm,trig-in-typesarm,trig-out-sigsarm,trig-out-typesarm,trig-conn-nameinterrupt-namesdevice_typebus-rangelinux,pci-domaindma-rangesmsi-parentiommu-map-maskiommu-mappolling-delaypolling-delay-passivethermal-sensors#dma-cellsi2c-sda-hold-time-nsserial0stdout-pathmethodentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-idle-statescapacity-dmips-mhzdynamic-power-coefficientinterrupt-affinitymbox-namesmboxesshmem#power-domain-cells#thermal-sensor-cells