Ð þí~]8xD(x $rockchip,rk3308-evbrockchip,rk3308 +7Rockchip RK3308 EVBaliases=/i2c@ff040000B/i2c@ff050000G/i2c@ff060000L/i2c@ff070000Q/serial@ff0a0000Y/serial@ff0b0000a/serial@ff0c0000i/serial@ff0d0000q/serial@ff0e0000y/spi@ff120000~/spi@ff130000ƒ/spi@ff140000cpus+cpu@0ˆcpuarm,cortex-a35”˜psci¦­¼ZÖêú cpu@1ˆcpuarm,cortex-a35”˜psciÖêúcpu@2ˆcpuarm,cortex-a35”˜psciÖêú cpu@3ˆcpuarm,cortex-a35”˜psciÖêú idle-statespscicpu-sleeparm,idle-state+<Sxdút„l2-cachecacheopp-table-0operating-points-v2…opp-408000000�Q– —~ð~ðr`¥œ@¶opp-600000000�#ÃF —~ð~ðr`¥œ@opp-816000000�0£, —£è£èr`¥œ@opp-1008000000�<Ü —*ˆ*ˆr`¥œ@arm-pmuarm,cortex-a35-pmu0ÂSTUVÍ external-mac-clock fixed-clockàúð€ ðmac_clkinpsci arm,psci-1.0Ÿsmctimerarm,armv8-timer0   xin24m fixed-clockàn6ðxin24mOgrf@ff000000&rockchip,rk3308-grfsysconsimple-mfd”ÿ€Kreboot-modesyscon-reboot-modeRBÃ'RBÃ3RBÃ?RBÃMRBà syscon@ff008000.rockchip,rk3308-usb2phy-grfsysconsimple-mfd”ÿ€@+usb2phy@100rockchip,rk3308-usb2phy”[k ¦H‚phyclk ðusb480m_phy Ždisabled otg-port$ÂCDE•otg-bvalidotg-idlinestate¥ Ždisabled9host-port ÂJ •linestate¥ Ždisabled:syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd”ÿ°+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd”ÿÀ+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c”ÿ¦Ê ‚i2cpclk  °default¾ + Ždisabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c”ÿ¦Ë ‚i2cpclk  °default¾ + Ždisabledi2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c”ÿ¦Ì ‚i2cpclk  °default¾+ Ždisabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c”ÿ¦Í ‚i2cpclk °default¾+ Ždisabledwatchdog@ff080000 rockchip,rk3308-wdtsnps,dw-wdt”ÿ¦Ö   Ždisabledserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart”ÿ  ¦łbaudclkapb_pclkÈÒ°default ¾ Ždisabledserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart”ÿ  ¦Ƃbaudclkapb_pclkÈÒ°default ¾ Ždisabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart”ÿ  ¦ǂbaudclkapb_pclkÈÒ°default¾ Ždisabledserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart”ÿ  ¦Ȃbaudclkapb_pclkÈÒ°default¾ Ždisabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart”ÿ ¦ɂbaudclkapb_pclkÈÒ°default¾Žokayspi@ff120000(rockchip,rk3308-spirockchip,rk3066-spi”ÿ Â+¦Ï‚spiclkapb_pclkßätxrx°default¾ Ždisabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spi”ÿ Â+¦Ð‚spiclkapb_pclkßätxrx°default¾ ! Ždisabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spi”ÿ Â+¦Ñ‚spiclkapb_pclkß""ätxrx°default¾#$%& Ždisabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ¦yè ‚pwmpclk°default¾'î Ždisabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ¦yè ‚pwmpclk°default¾(î Ždisabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ ¦yè ‚pwmpclk°default¾)î Ždisabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ0¦yè ‚pwmpclk°default¾*î Ždisabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ¦xç ‚pwmpclk°default¾+î Ždisabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ¦xç ‚pwmpclk°default¾,î Ždisabledpwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ ¦xç ‚pwmpclk°default¾-î Ždisabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ0¦xç ‚pwmpclk°default¾.î Ždisabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ¦Î ‚pwmpclk°default¾/îŽokaybpwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ¦Î ‚pwmpclk°default¾0î Ždisabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ ¦Î ‚pwmpclk°default¾1î Ždisabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm”ÿ0¦Î ‚pwmpclk°default¾2î Ždisabledrktimer@ff1a0000rockchip,rk3288-timer”ÿ  Â¦Ô ‚pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc”ÿ Â%¦%Ò‚saradcapb_pclkù F saradc-apbŽokay3[dma-controller@ff2c0000arm,pl330arm,primecell”ÿ,@Â*¦Š ‚apb_pclkAdma-controller@ff2d0000arm,pl330arm,primecell”ÿ-@Â*¦‹ ‚apb_pclkA"i2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s”ÿ5 Â4¦\¨‚i2s_clki2s_hclkß"" ätxrx •”reset-mreset-h°default¾4567 Ždisabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s”ÿ6 Â5¦^©‚i2s_clki2s_hclkß" ärx —–reset-mreset-h Ždisabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdif”ÿ: Â7¦b¢ ‚mclkhclkß" ätx°default¾8 Ždisabledusb@ff4000002rockchip,rk3308-usbrockchip,rk3066-usbsnps,dwc2”ÿ@ ÂB¦ž‚otgLotgTfu€€@ „9 ‰usb2-phy Ždisabledusb@ff440000 generic-ehci”ÿD ÂG¦Ÿ  „:‰usb Ždisabledusb@ff450000 generic-ohci”ÿE ÂH¦Ÿ  „:‰usb Ždisabledmmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshc”ÿH@ ÂL“ ¦š012‚biuciuciu-driveciu-sample�¨ðÑ€°default¾;<=> Ždisabledmmc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshc”ÿI@ ÂM“ ¦œ:;<‚biuciuciu-driveciu-sample�¨ðÑ€ Ždisabledmmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshc”ÿJ@ ÂN“ ¦›567‚biuciuciu-driveciu-sample�¨ðÑ€°default ¾?@A Ždisablednand-controller@ff4b0000(rockchip,rk3308-nfcrockchip,rv1108-nfc”ÿK@ ÂQ¦™-‚ahbnfc[-¶ðÑ€¾BCDEFGH°default Ždisabledethernet@ff4e0000rockchip,rk3308-gmac”ÿN Â@•macirq@¦@BBA@†ÃC[‚stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedËrmii°default¾IJ } stmmacethÔK Ždisabledspi@ff4c0000 rockchip,sfc”ÿL@ ÂR¦=�‚clk_sfchclk_sfc ¾LMN°default Ždisabledclock-controller@ff500000rockchip,rk3308-cru”ÿP¦O‚xin24mÔKá[¶€interrupt-controller@ff580000 arm,gic-400@”ÿXÿX ÿX@ ÿX`   îÿsram@fff80000 mmio-sram”ÿøÿø+ddr-sram@0”€vad-sram@8000”€€pinctrlrockchip,rk3308-pinctrlÔK+°default¾Pgpio@ff220000rockchip,gpio-bank”ÿ" Â(¦×+ÿî]gpio@ff230000rockchip,gpio-bank”ÿ# Â)¦Ø+ÿîgpio@ff240000rockchip,gpio-bank”ÿ$ Â*¦Ù+ÿîgpio@ff250000rockchip,gpio-bank”ÿ% Â+¦Ú+ÿîgpio@ff260000rockchip,gpio-bank”ÿ& Â,¦Û+ÿîpcfg-pull-up7Zpcfg-pull-downDWpcfg-pull-noneSSpcfg-pull-none-2maS`pcfg-pull-up-2ma7`pcfg-pull-up-4ma7`Ypcfg-pull-none-4maS`Xpcfg-pull-down-4maD`pcfg-pull-none-8maS`Qpcfg-pull-up-8ma7`Rpcfg-pull-none-12maS` Upcfg-pull-up-12ma7` Tpcfg-pull-none-smtSoVpcfg-output-high„pcfg-output-low�pcfg-input-high7›pcfg-input›emmcemmc-clk¨ Qemmc-cmd¨Remmc-pwren¨ Semmc-rstn¨ Semmc-bus1¨Remmc-bus4@¨RRRRemmc-bus8€¨RRRRRRRRflashflash-csn0¨ SEflash-rdy¨ SGflash-ale¨ SBflash-cle¨ SDflash-wrn¨SHflash-rdn¨ SFflash-bus8€¨TTTTTTTTCsfcsfc-bus4@¨SSSSNsfc-bus2 ¨SSsfc-cs0¨SMsfc-clk¨SLgmacrmii-pins�¨UUUSSSSS SImac-refclk-12ma¨ UJmac-refclk¨ Sgmac-m1rmiim1-pins�¨UUUSSSSS Smacm1-refclk-12ma¨ Umacm1-refclk¨ Si2c0i2c0-xfer ¨VV i2c1i2c1-xfer ¨ V V i2c2i2c2-xfer ¨VVi2c3-m0i2c3m0-xfer ¨VVi2c3-m1i2c3m1-xfer ¨ V Vi2c3-m2i2c3m2-xfer ¨VVi2s_2ch_0i2s-2ch-0-mclk¨ Si2s-2ch-0-sclk¨ S4i2s-2ch-0-lrck¨S5i2s-2ch-0-sdo¨S7i2s-2ch-0-sdi¨S6i2s_8ch_0i2s-8ch-0-mclk¨Si2s-8ch-0-sclktx¨Si2s-8ch-0-sclkrx¨Si2s-8ch-0-lrcktx¨Si2s-8ch-0-lrckrx¨Si2s-8ch-0-sdo0¨ Si2s-8ch-0-sdo1¨ Si2s-8ch-0-sdo2¨ Si2s-8ch-0-sdo3¨ Si2s-8ch-0-sdi0¨ Si2s-8ch-0-sdi1¨Si2s-8ch-0-sdi2¨Si2s-8ch-0-sdi3¨Si2s_8ch_1_m0i2s-8ch-1-m0-mclk¨Si2s-8ch-1-m0-sclktx¨Si2s-8ch-1-m0-sclkrx¨Si2s-8ch-1-m0-lrcktx¨Si2s-8ch-1-m0-lrckrx¨Si2s-8ch-1-m0-sdo0¨Si2s-8ch-1-m0-sdo1-sdi3¨Si2s-8ch-1-m0-sdo2-sdi2¨ Si2s-8ch-1-m0-sdo3_sdi1¨ Si2s-8ch-1-m0-sdi0¨ Si2s_8ch_1_m1i2s-8ch-1-m1-mclk¨ Si2s-8ch-1-m1-sclktx¨ Si2s-8ch-1-m1-sclkrx¨Si2s-8ch-1-m1-lrcktx¨Si2s-8ch-1-m1-lrckrx¨Si2s-8ch-1-m1-sdo0¨Si2s-8ch-1-m1-sdo1-sdi3¨Si2s-8ch-1-m1-sdo2-sdi2¨Si2s-8ch-1-m1-sdo3_sdi1¨Si2s-8ch-1-m1-sdi0¨Spdm_m0pdm-m0-clk¨Spdm-m0-sdi0¨ Spdm-m0-sdi1¨ Spdm-m0-sdi2¨ Spdm-m0-sdi3¨Spdm_m1pdm-m1-clk¨Spdm-m1-sdi0¨Spdm-m1-sdi1¨Spdm-m1-sdi2¨Spdm-m1-sdi3¨Spdm_m2pdm-m2-clkm¨Spdm-m2-clk¨Spdm-m2-sdi0¨ Spdm-m2-sdi1¨Spdm-m2-sdi2¨Spdm-m2-sdi3¨Spwm0pwm0-pin¨ Spwm0-pin-pull-down¨ W/pwm1pwm1-pin¨S0pwm1-pin-pull-down¨Wpwm2pwm2-pin¨S1pwm2-pin-pull-down¨Wpwm3pwm3-pin¨S2pwm3-pin-pull-down¨Wpwm4pwm4-pin¨S+pwm4-pin-pull-down¨Wpwm5pwm5-pin¨S,pwm5-pin-pull-down¨Wpwm6pwm6-pin¨S-pwm6-pin-pull-down¨Wpwm7pwm7-pin¨S.pwm7-pin-pull-down¨Wpwm8pwm8-pin¨ S'pwm8-pin-pull-down¨ Wpwm9pwm9-pin¨ S(pwm9-pin-pull-down¨ Wpwm10pwm10-pin¨ S)pwm10-pin-pull-down¨ Wpwm11pwm11-pin¨S*pwm11-pin-pull-down¨Wrtcrtc-32k¨SPsdmmcsdmmc-clk¨X;sdmmc-cmd¨Y<sdmmc-det¨Y=sdmmc-pwren¨Xsdmmc-bus1¨Ysdmmc-bus4@¨YYYY>sdiosdio-clk¨QAsdio-cmd¨R@sdio-pwren¨Qsdio-wrpt¨Qsdio-intn¨Qsdio-bus1¨Rsdio-bus4@¨RRRR?spdif_inspdif-in¨Sspdif_outspdif-out¨S8spi0spi0-clk¨Yspi0-csn0¨Yspi0-miso¨Yspi0-mosi¨Yspi1spi1-clk¨ Yspi1-csn0¨ Yspi1-miso¨ Y spi1-mosi¨ Y!spi1-m1spi1m1-miso¨Yspi1m1-mosi¨Yspi1m1-clk¨Yspi1m1-csn0¨ Yspi2spi2-clk¨Y#spi2-csn0¨Y$spi2-miso¨Y%spi2-mosi¨Y&tsadctsadc-otp-pin¨ Stsadc-otp-out¨ Suart0uart0-xfer ¨ZZuart0-cts¨Suart0-rts¨Suart0-rts-pin¨Suart1uart1-xfer ¨ZZuart1-cts¨Suart1-rts¨Suart2-m0uart2m0-xfer ¨ZZuart2-m1uart2m1-xfer ¨ZZuart3uart3-xfer ¨ Z Zuart3-m1uart3m1-xfer ¨ZZuart4uart4-xfer ¨ ZZuart4-cts¨Suart4-rts¨Suart4-rts-pin¨Sbuttonspwr-key¨Z\usbusb-drv¨Sasdio-pwrseqwifi-enable-h¨Schosen¶serial4:1500000n8adc-keys0 adc-keysÂ[Îbuttonsßdíw@func-keyÐ functionFPadc-keys1 adc-keysÂ[Îbuttonsßdíw@esc-keyømicmute>home-keyumode ¿ˆmenu-keyÏplay …€vol-down-keyr volume down“àvol-up-keys volume upFPgpio-keys gpio-keys2°default¾\power =]tGPIO Key PowerCdUvcc12v-dcinregulator-fixed cvcc12v_dcinr·Š·¢¶^vcc5v0-sysregulator-fixed cvcc5v0_sysrLK@ŠLK@¢¶È^`vcc-1v8regulator-fixedcvcc_1v8rw@Šw@¢¶È_3vcc-ddrregulator-fixedcvcc_ddrrã`Šã`¢¶È`vcc-ioregulator-fixedcvcc_ior2Z Š2Z ¢¶È`_vccio-flashregulator-fixed cvccio_flashr2Z Š2Z ¢¶È_vcc5v0-hostregulator-fixed Ó]ذdefault¾a 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootassigned-clocksassigned-clock-parentsclock-namesstatusinterrupt-names#phy-cellspinctrl-namespinctrl-0reg-shiftreg-io-widthdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesvref-supplyarm,pl330-periph-burst#dma-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesbus-widthfifo-depthmax-frequencyassigned-clock-ratesphy-moderockchip,grf#reset-cells#interrupt-cellsinterrupt-controllerrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathio-channelsio-channel-namespoll-intervalkeyup-threshold-microvoltlinux,codelabelpress-threshold-microvoltautorepeatgpiosdebounce-intervalwakeup-sourceregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplygpioenable-active-highpwmsregulator-settling-time-up-uspwm-supply