Ð þí|s8v4(?uü&firefly,roc-rk3308-ccrockchip,rk3308 +7Firefly ROC-RK3308-CC boardaliases=/i2c@ff040000B/i2c@ff050000G/i2c@ff060000L/i2c@ff070000Q/serial@ff0a0000Y/serial@ff0b0000a/serial@ff0c0000i/serial@ff0d0000q/serial@ff0e0000y/spi@ff120000~/spi@ff130000ƒ/spi@ff140000ˆ/mmc@ff480000�/mmc@ff490000cpus+cpu@0’cpuarm,cortex-a35ž¢psci°·ÆZàô cpu@1’cpuarm,cortex-a35ž¢psciàô cpu@2’cpuarm,cortex-a35ž¢psciàô cpu@3’cpuarm,cortex-a35ž¢psciàô idle-states(pscicpu-sleeparm,idle-state5F]xnú~„ l2-cachecache opp-table-0operating-points-v2� opp-408000000šQ– ¡~ð~ðr`¯œ@Àopp-600000000š#ÃF ¡~ð~ðr`¯œ@opp-816000000š0£, ¡£è£èr`¯œ@opp-1008000000š<Ü ¡*ˆ*ˆr`¯œ@arm-pmuarm,cortex-a35-pmu0ÌSTUV× external-mac-clock fixed-clockêúð€ úmac_clkin psci arm,psci-1.0©smctimerarm,armv8-timer0Ì   xin24m fixed-clock ên6úxin24m Rgrf@ff000000&rockchip,rk3308-grfsysconsimple-mfdžÿ€ Nreboot-modesyscon-reboot-mode!RBÃ1RBÃ=RBÃIRBÃWRBà syscon@ff008000.rockchip,rk3308-usb2phy-grfsysconsimple-mfdžÿ€@+usb2phy@100rockchip,rk3308-usb2phyžeu °HŒphyclk úusb480m_phy  ˜disabled otg-port$ÌCDEŸotg-bvalidotg-idlinestate¯ ˜disabled :host-port ÌJ Ÿlinestate¯ ˜disabled ;syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfdžÿ°+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfdžÿÀ+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2cžÿ°Ê Œi2cpclk Ì ºdefaultÈ + ˜disabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2cžÿ°Ë Œi2cpclk Ì ºdefaultÈ +˜okayê€rtc@51 nxp,pcf8563žQ i2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2cžÿ°Ì Œi2cpclk Ì ºdefaultÈ+ ˜disabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2cžÿ°Í Œi2cpclk ̺defaultÈ+ ˜disabledwatchdog@ff080000 rockchip,rk3308-wdtsnps,dw-wdtžÿ°Ö Ì  ˜disabledserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uartžÿ  ̰Ōbaudclkapb_pclkÒܺdefault È ˜disabledserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uartžÿ  ̰ƌbaudclkapb_pclkÒܺdefault È ˜disabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uartžÿ  ̰njbaudclkapb_pclkÒܺdefaultȘokayserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uartžÿ  ̰Ȍbaudclkapb_pclkÒܺdefaultÈ ˜disabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uartžÿ ̰Ɍbaudclkapb_pclkÒܺdefault È ˜disabledspi@ff120000(rockchip,rk3308-spirockchip,rk3066-spižÿ Ì+°ÏŒspiclkapb_pclkéîtxrxºdefaultÈ ˜disabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spižÿ Ì+°ÐŒspiclkapb_pclkéîtxrxºdefaultÈ !"# ˜disabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spižÿ Ì+°ÑŒspiclkapb_pclké$$îtxrxºdefaultÈ%&'( ˜disabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwmžÿ°yè ŒpwmpclkºdefaultÈ)ø ˜disabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwmžÿ°yè ŒpwmpclkºdefaultÈ*ø ˜disabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwmžÿ °yè ŒpwmpclkºdefaultÈ+ø ˜disabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwmžÿ0°yè ŒpwmpclkºdefaultÈ,ø ˜disabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwmžÿ°xç ŒpwmpclkºdefaultÈ-ø ˜disabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwmžÿ°xç ŒpwmpclkºactiveÈ.ø˜okay `pwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwmžÿ °xç ŒpwmpclkºdefaultÈ/ø ˜disabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwmžÿ0°xç ŒpwmpclkºdefaultÈ0ø ˜disabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwmžÿ°Î ŒpwmpclkºdefaultÈ1ø˜okay epwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwmžÿ°Î ŒpwmpclkºdefaultÈ2ø ˜disabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwmžÿ °Î ŒpwmpclkºdefaultÈ3ø ˜disabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwmžÿ0°Î ŒpwmpclkºdefaultÈ4ø ˜disabledrktimer@ff1a0000rockchip,rk3288-timeržÿ  Ì°Ô Œpclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradcžÿ Ì%°%ÒŒsaradcapb_pclkF saradc-apb ˜disableddma-controller@ff2c0000arm,pl330arm,primecellžÿ,@Ì(°Š Œapb_pclk? dma-controller@ff2d0000arm,pl330arm,primecellžÿ-@Ì(°‹ Œapb_pclk? $i2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2sžÿ5 Ì4°\¨Œi2s_clki2s_hclké$$ îtxrx•”reset-mreset-hºdefaultÈ5678 ˜disabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2sžÿ6 Ì5°^©Œi2s_clki2s_hclké$ îrx—–reset-mreset-h ˜disabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdifžÿ: Ì7°b¢ Œmclkhclké$ îtxºdefaultÈ9 ˜disabledusb@ff4000002rockchip,rk3308-usbrockchip,rk3066-usbsnps,dwc2žÿ@ ÌB°žŒotgJotgRds€€@ ‚: ‡usb2-phy ˜disabledusb@ff440000 generic-ehcižÿD ÌG°Ÿ  ‚;‡usb ˜disabledusb@ff450000 generic-ohcižÿE ÌH°Ÿ  ‚;‡usb ˜disabledmmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcžÿH@ ÌL‘ °š012Œbiuciuciu-driveciu-sample›¦ðÑ€ºdefaultÈ<=>?˜okay´Æ×,éö@Ammc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcžÿI@ ÌM‘ °œ:;<Œbiuciuciu-driveciu-sample›¦ðÑ€˜okay´*9mmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcžÿJ@ ÌN‘ °›567Œbiuciuciu-driveciu-sample›¦ðÑ€ºdefault ÈBCD ˜disablednand-controller@ff4b0000(rockchip,rk3308-nfcrockchip,rv1108-nfcžÿK@ ÌQ°™-Œahbnfce-GðÑ€ÈEFGHIJKºdefault ˜disabledethernet@ff4e0000rockchip,rk3308-gmacžÿN Ì@Ÿmacirq@°@BBA@†ÃC[Œstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed\rmiiºdefaultÈLM} stmmacetheN ˜disabledspi@ff4c0000 rockchip,sfcžÿL@ ÌR°=�Œclk_sfchclk_sfc ÈOPQºdefault ˜disabledclock-controller@ff500000rockchip,rk3308-cružÿP°RŒxin24meN reG€ interrupt-controller@ff580000 arm,gic-400@žÿXÿX ÿX@ ÿX`  Ì � sram@fff80000 mmio-sramžÿø¥ÿø+ddr-sram@0ž€vad-sram@8000ž€€pinctrlrockchip,rk3308-pinctrleN+¥ºdefaultÈSgpio@ff220000rockchip,gpio-bankžÿ" Ì(°×¬¼� ^gpio@ff230000rockchip,gpio-bankžÿ# Ì)°Ø¬¼�gpio@ff240000rockchip,gpio-bankžÿ$ Ì*°Ù¬¼�gpio@ff250000rockchip,gpio-bankžÿ% Ì+°Ú¬¼�gpio@ff260000rockchip,gpio-bankžÿ& Ì,°Û¬¼� cpcfg-pull-upÈ ]pcfg-pull-downÕ Zpcfg-pull-noneä Vpcfg-pull-none-2maäñpcfg-pull-up-2maÈñpcfg-pull-up-4maÈñ \pcfg-pull-none-4maäñ [pcfg-pull-down-4maÕñpcfg-pull-none-8maäñ Tpcfg-pull-up-8maÈñ Upcfg-pull-none-12maäñ  Xpcfg-pull-up-12maÈñ  Wpcfg-pull-none-smtä Ypcfg-output-highpcfg-output-low!pcfg-input-highÈ,pcfg-input,emmcemmc-clk9 Temmc-cmd9Uemmc-pwren9 Vemmc-rstn9 Vemmc-bus19Uemmc-bus4@9UUUUemmc-bus8€9UUUUUUUUflashflash-csn09 V Hflash-rdy9 V Jflash-ale9 V Eflash-cle9 V Gflash-wrn9V Kflash-rdn9 V Iflash-bus8€9WWWWWWWW Fsfcsfc-bus4@9VVVV Qsfc-bus2 9VVsfc-cs09V Psfc-clk9V Ogmacrmii-pins�9XXXVVVVV V Lmac-refclk-12ma9 X Mmac-refclk9 Vgmac-m1rmiim1-pins�9XXXVVVVV Vmacm1-refclk-12ma9 Xmacm1-refclk9 Vi2c0i2c0-xfer 9YY i2c1i2c1-xfer 9 Y Y i2c2i2c2-xfer 9YY i2c3-m0i2c3m0-xfer 9YY i2c3-m1i2c3m1-xfer 9 Y Yi2c3-m2i2c3m2-xfer 9YYi2s_2ch_0i2s-2ch-0-mclk9 Vi2s-2ch-0-sclk9 V 5i2s-2ch-0-lrck9V 6i2s-2ch-0-sdo9V 8i2s-2ch-0-sdi9V 7i2s_8ch_0i2s-8ch-0-mclk9Vi2s-8ch-0-sclktx9Vi2s-8ch-0-sclkrx9Vi2s-8ch-0-lrcktx9Vi2s-8ch-0-lrckrx9Vi2s-8ch-0-sdo09 Vi2s-8ch-0-sdo19 Vi2s-8ch-0-sdo29 Vi2s-8ch-0-sdo39 Vi2s-8ch-0-sdi09 Vi2s-8ch-0-sdi19Vi2s-8ch-0-sdi29Vi2s-8ch-0-sdi39Vi2s_8ch_1_m0i2s-8ch-1-m0-mclk9Vi2s-8ch-1-m0-sclktx9Vi2s-8ch-1-m0-sclkrx9Vi2s-8ch-1-m0-lrcktx9Vi2s-8ch-1-m0-lrckrx9Vi2s-8ch-1-m0-sdo09Vi2s-8ch-1-m0-sdo1-sdi39Vi2s-8ch-1-m0-sdo2-sdi29 Vi2s-8ch-1-m0-sdo3_sdi19 Vi2s-8ch-1-m0-sdi09 Vi2s_8ch_1_m1i2s-8ch-1-m1-mclk9 Vi2s-8ch-1-m1-sclktx9 Vi2s-8ch-1-m1-sclkrx9Vi2s-8ch-1-m1-lrcktx9Vi2s-8ch-1-m1-lrckrx9Vi2s-8ch-1-m1-sdo09Vi2s-8ch-1-m1-sdo1-sdi39Vi2s-8ch-1-m1-sdo2-sdi29Vi2s-8ch-1-m1-sdo3_sdi19Vi2s-8ch-1-m1-sdi09Vpdm_m0pdm-m0-clk9Vpdm-m0-sdi09 Vpdm-m0-sdi19 Vpdm-m0-sdi29 Vpdm-m0-sdi39Vpdm_m1pdm-m1-clk9Vpdm-m1-sdi09Vpdm-m1-sdi19Vpdm-m1-sdi29Vpdm-m1-sdi39Vpdm_m2pdm-m2-clkm9Vpdm-m2-clk9Vpdm-m2-sdi09 Vpdm-m2-sdi19Vpdm-m2-sdi29Vpdm-m2-sdi39Vpwm0pwm0-pin9 Vpwm0-pin-pull-down9 Z 1pwm1pwm1-pin9V 2pwm1-pin-pull-down9Zpwm2pwm2-pin9V 3pwm2-pin-pull-down9Zpwm3pwm3-pin9V 4pwm3-pin-pull-down9Zpwm4pwm4-pin9V -pwm4-pin-pull-down9Zpwm5pwm5-pin9Vpwm5-pin-pull-down9Z .pwm6pwm6-pin9V /pwm6-pin-pull-down9Zpwm7pwm7-pin9V 0pwm7-pin-pull-down9Zpwm8pwm8-pin9 V )pwm8-pin-pull-down9 Zpwm9pwm9-pin9 V *pwm9-pin-pull-down9 Zpwm10pwm10-pin9 V +pwm10-pin-pull-down9 Zpwm11pwm11-pin9V ,pwm11-pin-pull-down9Zrtcrtc-32k9V Ssdmmcsdmmc-clk9[ <sdmmc-cmd9\ =sdmmc-det9\ >sdmmc-pwren9[sdmmc-bus19\sdmmc-bus4@9\\\\ ?sdiosdio-clk9T Dsdio-cmd9U Csdio-pwren9Tsdio-wrpt9Tsdio-intn9Tsdio-bus19Usdio-bus4@9UUUU Bspdif_inspdif-in9Vspdif_outspdif-out9V 9spi0spi0-clk9\ spi0-csn09\ spi0-miso9\ spi0-mosi9\ spi1spi1-clk9 \ spi1-csn09 \ !spi1-miso9 \ "spi1-mosi9 \ #spi1-m1spi1m1-miso9\spi1m1-mosi9\spi1m1-clk9\spi1m1-csn09 \spi2spi2-clk9\ %spi2-csn09\ &spi2-miso9\ 'spi2-mosi9\ (tsadctsadc-otp-pin9 Vtsadc-otp-out9 Vuart0uart0-xfer 9]] uart0-cts9V uart0-rts9V uart0-rts-pin9Vuart1uart1-xfer 9]] uart1-cts9V uart1-rts9V uart2-m0uart2m0-xfer 9]] uart2-m1uart2m1-xfer 9]]uart3uart3-xfer 9 ] ] uart3-m1uart3m1-xfer 9]]uart4uart4-xfer 9 ]] uart4-cts9V uart4-rts9V uart4-rts-pin9Vir-receiverir-recv-pin9V _buttonspwr-key9]chosenGserial2:1500000n8ir_rxgpio-ir-receiver S^ºdefaultÈ_ir_tx pwm-ir-txY`a¨leds gpio-ledsled-0^firefly:red:powerdir-power-clickzon S^led-1^firefly:blue:userdir-user-clickzoff S^ typec-vcc5vregulator-fixed ˆtypec_vcc5v—LK@¯LK@ÇÛ avcc5v0-sysregulator-fixed ˆvcc5v0_sys—LK@¯LK@ÇÛía bvcc-ioregulator-fixedˆvcc_io—2Z ¯2Z ÇÛíb dvcc-sdmmcregulator-gpio ˆvcc_sdmmc—w@¯2Z  S^ýw@2Z íb Avcc-sdregulator-fixed øcˆvcc_sd—2Z ¯2Z ÇÛíd @vdd-corepwm-regulatorYeˆ ˆvdd_core— žx¯r`ý|ØúÇÛ4b vdd-logregulator-fixedˆvdd_log—�¯�ÇÛíb compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootassigned-clocksassigned-clock-parentsclock-namesstatusinterrupt-names#phy-cellspinctrl-namespinctrl-0reg-shiftreg-io-widthdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesarm,pl330-periph-burst#dma-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-hs200-1_8vnon-removableassigned-clock-ratesphy-moderockchip,grf#reset-cells#interrupt-cellsinterrupt-controllerrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathgpiospwmslabellinux,default-triggerdefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplygpioregulator-init-microvoltregulator-settling-time-up-uspwm-supply