Ð þí‹‚8�d( �,azw,beelink-a1rockchip,rk3328 + 7Beelink A1aliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000}/mmc@ff500000‚/mmc@ff520000cpus+cpu@0‡cpuarm,cortex-a53“—ž­½x×psciåö  cpu@1‡cpuarm,cortex-a53“—ž­½x×psciåö  cpu@2‡cpuarm,cortex-a53“—ž­½x×psciåö  cpu@3‡cpuarm,cortex-a53“—ž­½x×psciåö  idle-statespscicpu-sleeparm,idle-state*;Rxcús„l2-cache0cacheopp-table-0operating-points-v2„opp-408000000�Q––~ð¤œ@µopp-600000000�#ÃF–~ð¤œ@opp-816000000�0£,–B@¤œ@opp-1008000000�<Ü–Èज@opp-1200000000�G†Œ–±(¤œ@opp-1296000000�M?d–Ö ¤œ@analog-soundsimple-audio-cardÁi2sÚ ôAnalog A/V okaysimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg' display-subsystemrockchip,display-subsystem: hdmi-soundsimple-audio-cardÁi2sÚ€ôHDMI okaysimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2Þsmctimerarm,armv8-timer0   xin24m fixed-clock@Mn6]xin24mFi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s“ÿ —)7pi2s_clki2s_hclk|  �txrx‹ okayi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s“ÿ —*8pi2s_clki2s_hclk|�txrx‹ okayi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s“ÿ —+9pi2s_clki2s_hclk|�txrx‹  disabledspdif@ff030000rockchip,rk3328-spdif“ÿ —.: pmclkhclk| �txœdefaultª‹  disabledpdm@ff040000 rockchip,pdm“ÿ—=Rppdm_clkpdm_hclk|�rxœdefaultsleepª´  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd“ÿ9io-domains"rockchip,rk3328-io-voltage-domain okay¾ÌÚèögpiorockchip,rk3328-grf-gpio/Epower-controller!rockchip,rk3328-power-controller;+<power-domain@6“;power-domain@5“ —‹BAB;power-domain@8“—�F;reboot-modesyscon-reboot-modeOÈVRBÃbRBÃpRBà €RBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart“ÿ 7—&Òpbaudclkapb_pclk|�txrxœdefault ª !Œ™  disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart“ÿ 8—'Ópbaudclkapb_pclk|�txrxœdefault ª"#$Œ™  disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart“ÿ 9—(Ôpbaudclkapb_pclk|�txrxœdefaultª%Œ™ okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ $+—7Í pi2cpclkœdefaultª&  disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ %+—8Î pi2cpclkœdefaultª' okayMB@£»Spmic@18rockchip,rk805“ (œdefaultª)Òó@* **%*1=regulatorsDCDC_REG1 Ivdd_logicX ®`p™pˆœ:regulator-state-mem®ÆB@DCDC_REG2Ivdd_armX ®`p™pˆœregulator-state-mem®Æ~ðDCDC_REG3Ivcc_ddrˆœregulator-state-mem®DCDC_REG4Ivcc_ioX2Z p2Z ˆœregulator-state-mem®Æ2Z LDO_REG1Ivdd_18Xw@pw@ˆœregulator-state-mem®Æw@LDO_REG2 Ivcc_18emmcXw@pw@ˆœregulator-state-mem®Æw@LDO_REG3Ivdd_11XÈàpÈàˆœregulator-state-mem®ÆÈài2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ &+—9Ï pi2cpclkœdefaultª+  disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ '+—:Ð pi2cpclkœdefaultª,  disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi“ÿ 1+— Ñpspiclkapb_pclk| �txrxœdefaultª-./0  disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt“ÿ (—ìpwm@ff1b0000rockchip,rk3328-pwm“ÿ—<Ö ppwmpclkœdefaultª1â  disabledpwm@ff1b0010rockchip,rk3328-pwm“ÿ—<Ö ppwmpclkœdefaultª2â  disabledpwm@ff1b0020rockchip,rk3328-pwm“ÿ —<Ö ppwmpclkœdefaultª3â  disabledpwm@ff1b0030rockchip,rk3328-pwm“ÿ0 2—<Ö ppwmpclkœdefaultª4â  disableddma-controller@ff1f0000arm,pl330arm,primecell“ÿ@í—† papb_pclkthermal-zonessoc-thermal%è3èE5tripstrip-point0UpaÐŽpassivetrip-point1ULaÐŽpassive6soc-critUsaÐ Žcriticalcooling-mapsmap0l60q ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ€tsadc@ff250000rockchip,rk3328-tsadc“ÿ% :�$�ÃP—$Õptsadcapb_pclkœinitdefaultsleepª7´8²7¼B Ãtsadc-apbÏ9܆ ó okay  5efuse@ff260000rockchip,rk3328-efuse“ÿ&P+—> ppclk_efuse; id@7“cpu-leakage@17“logic-leakage@19“cpu-version@1a“OGadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc“ÿ( PT—%êpsaradcapb_pclk¼V Ãsaradc-apb  disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-450“ÿ0TZW]XY[\"fgpgpmmupppp0ppmmu0pp1ppmmu1—‡‡ pbuscore¼fv:iommu@ff330200rockchip,iommu“ÿ3 `—“Ý paclkiface‚  disablediommu@ff340800rockchip,iommu“ÿ4@ b—�F paclkiface‚  disabledvideo-codec@ff350000rockchip,rk3328-vpu“ÿ5  fvdpu—�F paclkhclk�;–<iommu@ff350800rockchip,iommu“ÿ5@  —�F paclkiface‚–<;video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec“ÿ6  —‹BABpaxiahbcabaccore�‹AB �ׄׄá£�=–<iommu@ff360480rockchip,iommu “ÿ6€@ÿ6À@ J—‹B paclkiface‚–<=vop@ff370000rockchip,rk3328-vop“ÿ7>ü  —‘x;paclk_vopdclk_vophclk_vop¼…†‡ Ãaxiahbdclk�> okayport+ endpoint@0“¤?Diommu@ff373f00rockchip,iommu“ÿ7?  —‘; paclkiface‚ okay>hdmi@ff3c0000rockchip,rk3328-dw-hdmi“ÿ<Œ#G—çFpiahbisfrcec´@¹hdmiœdefault ªABCÏ9‹ okayportsportendpoint¤D?codec@ff410000rockchip,rk3328-codec“ÿA—ë* ppclkmclkÏ9‹ okay ÃEphy@ff430000rockchip,rk3328-hdmi-phy“ÿC S—äFypsysclkrefoclkrefpclk ]hdmi_phy@ÎG Úcpu-versionë okay@clock-controller@ff440000(rockchip,rk3328-crurockchip,crusyscon“ÿDÏ9@öø�x=&'(ˆ‰Ž…ƒŠŒ�ABDC"\5ˆH؉4æ$zFFF|�©€n6n6n6äáÀäáÀõáõáõáõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd“ÿE+usb2phy@100rockchip,rk3328-usb2phy“—Fpphyclk ]usb480m_phy@�{H okayHotg-portë$;<=fotg-bvalidotg-idlinestate okayVhost-portë > flinestate okayWmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc“ÿP@   —=!JNpbiuciuciu-driveciu-sample%ðÑ€ okay3=O`œdefaultªIJKLkwmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc“ÿQ@   —>"KOpbiuciuciu-driveciu-sample%ðÑ€  disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc“ÿR@  —?#LPpbiuciuciu-driveciu-sample%ðÑ€ okay3=„‘ ¦®œdefault ªMNOkwethernet@ff540000rockchip,rk3328-gmac“ÿT fmacirq8—dWXZY–ßMpstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac¼c ÃstmmacethÏ9¼ okay�dfPPÇinputÔQßrgmiièœdefaultªRóü&mdiosnps,dwmac-mdio+ethernet-phy@0“''u0 9(Qethernet@ff550000rockchip,rk3328-gmac“ÿUÏ9 fmacirq8—TSSU•ÞVIpstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy¼b ÃstmmacethßrmiiÔS¼Çoutput  disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22“—V¼dœdefaultªTUESusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2“ÿX —MpotgWhost_q€€€@ ´V ¹usb2-phy okayusb@ff5c0000 generic-ehci“ÿ\  —NH´W¹usb okayœdefaultªXYZ[\]usb@ff5d0000 generic-ohci“ÿ]  —NH´W¹usb  disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3“ÿ` C—`a„pref_clksuspend_clkbus_clkWotg �utmi_wide˜¹Ñó  -  disabledinterrupt-controller@ff811000 arm,gic-400 F W@“ÿ�ÿ� ÿ�@ ÿ�`   pinctrlrockchip,rk3328-pinctrlÏ9+ lgpio@ff210000rockchip,gpio-bank“ÿ! 3—È/ W Fkgpio@ff220000rockchip,gpio-bank“ÿ" 4—É/ W Fgpio@ff230000rockchip,gpio-bank“ÿ# 5—Ê/ W F(gpio@ff240000rockchip,gpio-bank“ÿ$ 6—Ë/ W Fpcfg-pull-up s`pcfg-pull-down €hpcfg-pull-none �^pcfg-pull-none-2ma � œgpcfg-pull-up-2ma s œpcfg-pull-up-4ma s œapcfg-pull-none-4ma � œdpcfg-pull-down-4ma € œpcfg-pull-none-8ma � œbpcfg-pull-up-8ma s œcpcfg-pull-none-12ma � œ epcfg-pull-up-12ma s œ fpcfg-output-high «jpcfg-output-low ·ipcfg-input-high s Â_pcfg-input Âi2c0i2c0-xfer Ï^^&i2c1i2c1-xfer Ï^^'i2c2i2c2-xfer Ï ^^+i2c3i2c3-xfer Ï^^,i2c3-pins Ï^^hdmi_i2chdmii2c-xfer Ï^^Bpdm-0pdmm0-clk Ï^pdmm0-fsync Ï^pdmm0-sdi0 Ï^pdmm0-sdi1 Ï^pdmm0-sdi2 Ï^pdmm0-sdi3 Ï^pdmm0-clk-sleep Ï_pdmm0-sdi0-sleep Ï_pdmm0-sdi1-sleep Ï_pdmm0-sdi2-sleep Ï_pdmm0-sdi3-sleep Ï_pdmm0-fsync-sleep Ï_tsadcotp-pin Ï ^7otp-out Ï ^8uart0uart0-xfer Ï ^`uart0-cts Ï ^ uart0-rts Ï ^!uart0-rts-pin Ï ^uart1uart1-xfer Ï^`"uart1-cts Ï^#uart1-rts Ï^$uart1-rts-pin Ï^uart2-0uart2m0-xfer Ï^`uart2-1uart2m1-xfer Ï^`%spi0-0spi0m0-clk Ï`spi0m0-cs0 Ï `spi0m0-tx Ï `spi0m0-rx Ï `spi0m0-cs1 Ï `spi0-1spi0m1-clk Ï`spi0m1-cs0 Ï`spi0m1-tx Ï`spi0m1-rx Ï`spi0m1-cs1 Ï`spi0-2spi0m2-clk Ï`-spi0m2-cs0 Ï`0spi0m2-tx Ï`.spi0m2-rx Ï`/i2s1i2s1-mclk Ï^i2s1-sclk Ï^i2s1-lrckrx Ï^i2s1-lrcktx Ï^i2s1-sdi Ï^i2s1-sdo Ï^i2s1-sdio1 Ï^i2s1-sdio2 Ï^i2s1-sdio3 Ï^i2s1-sleep� Ï_________i2s2-0i2s2m0-mclk Ï^i2s2m0-sclk Ï^i2s2m0-lrckrx Ï^i2s2m0-lrcktx Ï^i2s2m0-sdi Ï^i2s2m0-sdo Ï^i2s2m0-sleep` Ï______i2s2-1i2s2m1-mclk Ï^i2s2m1-sclk Ï^i2sm1-lrckrx Ï^i2s2m1-lrcktx Ï^i2s2m1-sdi Ï^i2s2m1-sdo Ï^i2s2m1-sleepP Ï_____spdif-0spdifm0-tx Ï^spdif-1spdifm1-tx Ï^spdif-2spdifm2-tx Ï^sdmmc0-0sdmmc0m0-pwren Ïasdmmc0m0-pin Ïasdmmc0-1sdmmc0m1-pwren Ïasdmmc0m1-pin Ïasdmmc0sdmmc0-clk ÏbIsdmmc0-cmd ÏcJsdmmc0-dectn ÏaKsdmmc0-wrprt Ïasdmmc0-bus1 Ïcsdmmc0-bus4@ ÏccccLsdmmc0-pins€ Ïaaaaaaaasdmmc0extsdmmc0ext-clk Ïdsdmmc0ext-cmd Ïasdmmc0ext-wrprt Ïasdmmc0ext-dectn Ïasdmmc0ext-bus1 Ïasdmmc0ext-bus4@ Ïaaaasdmmc0ext-pins€ Ïaaaaaaaasdmmc1sdmmc1-clk Ï bsdmmc1-cmd Ï csdmmc1-pwren Ïcsdmmc1-wrprt Ïcsdmmc1-dectn Ïcsdmmc1-bus1 Ïcsdmmc1-bus4@ Ïccccsdmmc1-pins� Ï a aaaaaaaaemmcemmc-clk ÏeMemmc-cmd ÏfNemmc-pwren Ï^emmc-rstnout Ï^emmc-bus1 Ïfemmc-bus4@ Ïffffemmc-bus8€ ÏffffffffOpwm0pwm0-pin Ï^1pwm1pwm1-pin Ï^2pwm2pwm2-pin Ï^3pwmirpwmir-pin Ï^4gmac-1rgmiim1-pins` Ï b ddbddd d db bddbbb bdbbbbRrmiim1-pins Ïgegggg g ge e ^ ^^^^^gmac2phyfephyled-speed10 Ï^fephyled-duplex Ï^fephyled-rxm1 Ï^Tfephyled-txm1 Ï^fephyled-linkm1 Ï^Utsadc_pintsadc-int Ï ^tsadc-pin Ï ^hdmi_pinhdmi-cec Ï^Ahdmi-hpd ÏhCcif-0dvp-d2d9-m0À Ï^^^^^ ^ ^ ^^^^^cif-1dvp-d2d9-m1À Ï^^^^^^^^^^^^pmicpmic-int-l Ï`)usb3usb30-host-drv Ï^lwifibt-dis ÏiXbt-wake-host Ï`Ychip-en ÏiZhost-wake-bt Ïj[wl-dis Ïi\wl-wake-host Ï`]chosen Ýserial2:1500000n8external-gmac-clock fixed-clockMsY@ ]gmac_clkin@Pusb3-current-switchregulator-fixed é ükœdefaultªl Ivcc_host_5v *vcc-sysregulator-fixedIvcc_sysXLK@pLK@*ir-receivergpio-ir-receiver È( rc-beelink-gs1 compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shifti2c-scl-falling-time-nsi2c-scl-rising-time-nsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-namesmali-supply#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesmute-gpiosnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vno-sdno-sdionon-removablesnps,txpblclock_in_outphy-handlephy-modephy-supplysnps,aalsnps,pbltx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathenable-active-highgpiovin-supplylinux,rc-map-name