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fixed-clock;Hn6Xxin24mEi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2sŽÿ ’)7ki2s_clki2s_hclkw  |txrx† disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2sŽÿ ’*8ki2s_clki2s_hclkw|txrx† disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2sŽÿ ’+9ki2s_clki2s_hclkw|txrx† disabledspdif@ff030000rockchip,rk3328-spdifŽÿ ’.: kmclkhclkw |tx—default¥† disabledpdm@ff040000 rockchip,pdmŽÿ’=Rkpdm_clkpdm_hclkw|rx—defaultsleep¥¯ disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfdŽÿ:io-domains"rockchip,rk3328-io-voltage-domainokay¹ÆÔâðþ gpiorockchip,rk3328-grf-gpio*power-controller!rockchip,rk3328-power-controller6+<power-domain@6Ž6power-domain@5Ž ’‹BAB6power-domain@8Ž’�F6reboot-modesyscon-reboot-modeJÈQRBÃ]RBÃkRBà {RBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uartŽÿ 7’&Òkbaudclkapb_pclkw|txrx—default ¥ !"‡” disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uartŽÿ 8’'Ókbaudclkapb_pclkw|txrx—default ¥#$%‡” disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uartŽÿ 9’(Ôkbaudclkapb_pclkw|txrx—default¥&‡”okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2cŽÿ $+’7Í ki2cpclk—default¥' disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2cŽÿ %+’8Î ki2cpclk—default¥(okaypmic@18rockchip,rk805Ž );Xxin32krk805-clkout2*¥*—defaultž¿Í+Ù+å+ñ+ý +regulatorsDCDC_REG1vdd_log$8J ß4b z0Ôregulator-state-mem�§B@DCDC_REG2vdd_arm$8J ß4b z0Ôregulator-state-mem�§~ðDCDC_REG3vcc_ddr$8regulator-state-mem�DCDC_REG4 vcc_io_33$8J2Z b2Z regulator-state-mem�§2Z LDO_REG1vcc_18$8Jw@bw@regulator-state-mem�§w@LDO_REG2 vcc18_emmc$8Jw@bw@regulator-state-mem�§w@LDO_REG3vdd_10$8JB@bB@regulator-state-mem�§B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2cŽÿ &+’9Ï ki2cpclk—default¥, disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2cŽÿ '+’:Ð ki2cpclk—default¥- disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spiŽÿ 1+’ Ñkspiclkapb_pclkw |txrx—default¥./01 disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdtŽÿ (’ìpwm@ff1b0000rockchip,rk3328-pwmŽÿ’<Ö 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Hpcfg-pull-none-8ma ; HZpcfg-pull-up-8ma  H[pcfg-pull-none-12ma ; H ]pcfg-pull-up-12ma  H ^pcfg-output-high Wpcfg-output-low cpcfg-input-high  nWpcfg-input ni2c0i2c0-xfer {VV'i2c1i2c1-xfer {VV(i2c2i2c2-xfer { VV,i2c3i2c3-xfer {VV-i2c3-pins {VVhdmi_i2chdmii2c-xfer {VVBpdm-0pdmm0-clk {Vpdmm0-fsync {Vpdmm0-sdi0 {Vpdmm0-sdi1 {Vpdmm0-sdi2 {Vpdmm0-sdi3 {Vpdmm0-clk-sleep {Wpdmm0-sdi0-sleep {Wpdmm0-sdi1-sleep {Wpdmm0-sdi2-sleep {Wpdmm0-sdi3-sleep {Wpdmm0-fsync-sleep {Wtsadcotp-pin { V8otp-out { V9uart0uart0-xfer { VX uart0-cts { V!uart0-rts { V"uart0-rts-pin { Vuart1uart1-xfer {VX#uart1-cts {V$uart1-rts {V%uart1-rts-pin {Vuart2-0uart2m0-xfer {VXuart2-1uart2m1-xfer {VX&spi0-0spi0m0-clk {Xspi0m0-cs0 { Xspi0m0-tx { Xspi0m0-rx { Xspi0m0-cs1 { Xspi0-1spi0m1-clk {Xspi0m1-cs0 {Xspi0m1-tx {Xspi0m1-rx {Xspi0m1-cs1 {Xspi0-2spi0m2-clk {X.spi0m2-cs0 {X1spi0m2-tx {X/spi0m2-rx {X0i2s1i2s1-mclk {Vi2s1-sclk {Vi2s1-lrckrx {Vi2s1-lrcktx {Vi2s1-sdi {Vi2s1-sdo {Vi2s1-sdio1 {Vi2s1-sdio2 {Vi2s1-sdio3 {Vi2s1-sleep� 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{_]____ _ _] ] V VVVVVgmac2phyfephyled-speed10 {Vfephyled-duplex {Vfephyled-rxm1 {VRfephyled-txm1 {Vfephyled-linkm1 {VStsadc_pintsadc-int { Vtsadc-pin { Vhdmi_pinhdmi-cec {VAhdmi-hpd {`Ccif-0dvp-d2d9-m0À {VVVVV V V VVVVVcif-1dvp-d2d9-m1À {VVVVVVVVVVVVbuttonreset-button-pin {Vagmac2ioeth-phy-reset-pin {`Pledslan-led-pin {Vcsys-led-pin {Vdwan-led-pin {Velanlan-vdd-pin {Vipmicpmic-int-l {X*sdsdio-vcc-pin {Xgchosen ‰serial2:1500000n8gmac-clock fixed-clockHsY@ Xgmac_clkin;Mkeys gpio-keys¥a—defaultreset •reset ëb ›˜ ¦2leds gpio-leds ¥cde—defaultled-0 ëf •nanopi-r2s:green:lanled-1 ëb •nanopi-r2s:red:sys ¸onled-2 ëf •nanopi-r2s:green:wansdmmcio-regulatorregulator-gpio Æ ë)¥g—default vcc_io_sdio$Jw@b2Z  Ùˆ ôvoltage бw@2Z  sdmmc-regulatorregulator-fixed b¥h—defaultvcc_sd8J2Z b2Z  Lvdd-5vregulator-fixedvdd_5v$8JLK@bLK@+vdd-5v-lanregulator-fixed Æ f¥i—default vdd_5v_lan$8 + compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplysnps,txpblclock_in_outphy-handlephy-modephy-supplyrx_delaysnps,aaltx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathlabellinux,codedebounce-intervaldefault-stateenable-active-highregulator-settling-time-usregulator-typestartup-delay-usvin-supplygpio