Ð þí�÷8†\( ›†$&firefly,roc-rk3328-pcrockchip,rk3328 +7Firefly ROC-RK3328-PCaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000}/mmc@ff500000‚/mmc@ff520000cpus+cpu@0‡cpuarm,cortex-a53“—ž­½x×psciåö  cpu@1‡cpuarm,cortex-a53“—ž­½x×psciåö  cpu@2‡cpuarm,cortex-a53“—ž­½x×psciåö  cpu@3‡cpuarm,cortex-a53“—ž­½x×psciåö  idle-statespscicpu-sleeparm,idle-state*;Rxcús„l2-cache0cacheopp-table-0operating-points-v2„opp-408000000�Q––~ð¤œ@µopp-600000000�#ÃF–~ð¤œ@opp-816000000�0£,–B@¤œ@opp-1008000000�<Ü–Èज@opp-1200000000�G†Œ–±(¤œ@opp-1296000000�M?d–Ö ¤œ@analog-soundsimple-audio-cardÁi2sÚôAnalog okaysimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg' display-subsystemrockchip,display-subsystem: hdmi-soundsimple-audio-cardÁi2sÚ€ôHDMI okaysimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2Þsmctimerarm,armv8-timer0   xin24m fixed-clock@Mn6]xin24mGi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s“ÿ —)7pi2s_clki2s_hclk|  �txrx‹ okayi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s“ÿ —*8pi2s_clki2s_hclk|�txrx‹ okayi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s“ÿ —+9pi2s_clki2s_hclk|�txrx‹  disabledspdif@ff030000rockchip,rk3328-spdif“ÿ —.: pmclkhclk| �txœdefaultª‹  disabledpdm@ff040000 rockchip,pdm“ÿ—=Rppdm_clkpdm_hclk|�rxœdefaultsleepª´  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd“ÿ:io-domains"rockchip,rk3328-io-voltage-domain okay¾ÌÚèögpiorockchip,rk3328-grf-gpio/Fpower-controller!rockchip,rk3328-power-controller;+=power-domain@6“;power-domain@5“ —‹BAB;power-domain@8“—�F;reboot-modesyscon-reboot-modeOÈVRBÃbRBÃpRBà €RBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart“ÿ 7—&Òpbaudclkapb_pclk|�txrxœdefault ª !"Œ™  disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart“ÿ 8—'Ópbaudclkapb_pclk|�txrxœdefault ª#$%Œ™  disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart“ÿ 9—(Ôpbaudclkapb_pclk|�txrxœdefaultª&Œ™ okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ $+—7Í pi2cpclkœdefaultª'  disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ %+—8Î pi2cpclkœdefaultª( okaypmic@18rockchip,rk805“ )@]xin32krk805-clkout2/œdefaultª*£ÄÒ+Þ+ê+ö+jregulatorsDCDC_REG1 vdd_logic) ß4A Ym;regulator-state-mem—B@DCDC_REG2vdd_arm) ß4A Ymregulator-state-mem—~ðDCDC_REG3vcc_ddrYmregulator-state-memDCDC_REG4vcc_io)2Z A2Z Ymregulator-state-mem—2Z LDO_REG1vcc_18)w@Aw@Ymregulator-state-mem—w@LDO_REG2 vcc18_emmc)w@Aw@Ymregulator-state-mem—w@LDO_REG3vdd_10)B@AB@Ymregulator-state-mem—B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ &+—9Ï pi2cpclkœdefaultª,  disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ '+—:Ð pi2cpclkœdefaultª-  disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi“ÿ 1+— Ñpspiclkapb_pclk| �txrxœdefaultª./01  disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt“ÿ (—ìpwm@ff1b0000rockchip,rk3328-pwm“ÿ—<Ö ppwmpclkœdefaultª2³  disabledpwm@ff1b0010rockchip,rk3328-pwm“ÿ—<Ö ppwmpclkœdefaultª3³  disabledpwm@ff1b0020rockchip,rk3328-pwm“ÿ —<Ö ppwmpclkœdefaultª4³  disabledpwm@ff1b0030rockchip,rk3328-pwm“ÿ0 2—<Ö ppwmpclkœdefaultª5³  disableddma-controller@ff1f0000arm,pl330arm,primecell“ÿ@¾—† papb_pclkÕthermal-zonessoc-thermalàöèè6tripstrip-point0&p2ÐŽpassivetrip-point1&L2ÐŽpassive7soc-crit&s2Ð Žcriticalcooling-mapsmap0=70B ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿQtsadc@ff250000rockchip,rk3328-tsadc“ÿ% :^$nÃP—$Õptsadcapb_pclkœinitdefaultsleepª8´9ƒ8�B ”tsadc-apb :­† Ä okay6efuse@ff260000rockchip,rk3328-efuse“ÿ&P+—> ppclk_efuseÚ id@7“cpu-leakage@17“logic-leakage@19“cpu-version@1a“îHadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc“ÿ( Pó—%êpsaradcapb_pclk�V ”saradc-apb okaykgpu@ff300000"rockchip,rk3328-maliarm,mali-450“ÿ0TZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1—‡‡ pbuscore�f!;iommu@ff330200rockchip,iommu“ÿ3 `—“Ý paclkiface-  disablediommu@ff340800rockchip,iommu“ÿ4@ b—�F paclkiface-  disabledvideo-codec@ff350000rockchip,rk3328-vpu“ÿ5  vdpu—�F paclkhclk:<A=iommu@ff350800rockchip,iommu“ÿ5@  —�F paclkiface-A=<video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec“ÿ6  —‹BABpaxiahbcabaccore^‹AB nׄׄá£:>A=iommu@ff360480rockchip,iommu “ÿ6€@ÿ6À@ J—‹B paclkiface-A=>vop@ff370000rockchip,rk3328-vop“ÿ7>ü  —‘x;paclk_vopdclk_vophclk_vop�…†‡ ”axiahbdclk:? okayport+ endpoint@0“O@Eiommu@ff373f00rockchip,iommu“ÿ7?  —‘; paclkiface- okay?hdmi@ff3c0000rockchip,rk3328-dw-hdmi“ÿ<Œ#G—çFpiahbisfrcec_Adhdmiœdefault ªBCD :‹ okayportsportendpointOE@codec@ff410000rockchip,rk3328-codec“ÿA—ë* ppclkmclk :‹ okay nFphy@ff430000rockchip,rk3328-hdmi-phy“ÿC S—äGypsysclkrefoclkrefpclk ]hdmi_phy@yH …cpu-version– okayAclock-controller@ff440000(rockchip,rk3328-crurockchip,crusyscon“ÿD :@¡ø^x=&'(ˆ‰Ž…ƒŠŒ�ABDC"\5ˆH؉4æ$®zGGG|n©€n6n6n6äáÀäáÀõáõáõáõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd“ÿE+usb2phy@100rockchip,rk3328-usb2phy“—Gpphyclk ]usb480m_phy@^{®I okayIotg-port–$;<=otg-bvalidotg-idlinestate okayYhost-port– > linestate okayZmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc“ÿP@   —=!JNpbiuciuciu-driveciu-sampleÅÐðÑ€ okayÞèú œdefaultªJKLM#0=KNWmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc“ÿQ@   —>"KOpbiuciuciu-driveciu-sampleÅÐðÑ€  disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc“ÿR@  —?#LPpbiuciuciu-driveciu-sampleÅÐðÑ€ okayÞèdq€œdefault ªOPQKWethernet@ff540000rockchip,rk3328-gmac“ÿT macirq8—dWXZY–ßMpstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac�c ”stmmaceth :Ž okay^df®RR™input¦S±rgmiiœdefaultªTº ÃUÓ é'ÃPþ $ethernet@ff550000rockchip,rk3328-gmac“ÿU : macirq8—TSSU•ÞVIpstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy�b ”stmmaceth±rmiiVŽ™output  disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22“—V�dœdefaultªWX&Vusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2“ÿX —Mpotg8host@Ra€€@ _Y dusb2-phy okayusb@ff5c0000 generic-ehci“ÿ\  —NI_Zdusb okayusb@ff5d0000 generic-ohci“ÿ]  —NI_Zdusb okayusb@ff600000rockchip,rk3328-dwc3snps,dwc3“ÿ` C—`a„pref_clksuspend_clkbus_clk8host putmi_wideyš²Ôõ  okayinterrupt-controller@ff811000 arm,gic-400 ' 8@“ÿ�ÿ� ÿ�@ ÿ�`   pinctrlrockchip,rk3328-pinctrl :+ Mgpio@ff210000rockchip,gpio-bank“ÿ! 3—È/ 8 ')gpio@ff220000rockchip,gpio-bank“ÿ" 4—É/ 8 'Ugpio@ff230000rockchip,gpio-bank“ÿ# 5—Ê/ 8 'lgpio@ff240000rockchip,gpio-bank“ÿ$ 6—Ë/ 8 'ppcfg-pull-up T]pcfg-pull-down aepcfg-pull-none p[pcfg-pull-none-2ma p }dpcfg-pull-up-2ma T }pcfg-pull-up-4ma T }^pcfg-pull-none-4ma p }apcfg-pull-down-4ma a }pcfg-pull-none-8ma p }_pcfg-pull-up-8ma T }`pcfg-pull-none-12ma p } bpcfg-pull-up-12ma T } cpcfg-output-high Œpcfg-output-low ˜pcfg-input-high T £\pcfg-input £i2c0i2c0-xfer °[['i2c1i2c1-xfer °[[(i2c2i2c2-xfer ° [[,i2c3i2c3-xfer °[[-i2c3-pins °[[hdmi_i2chdmii2c-xfer °[[Cpdm-0pdmm0-clk °[pdmm0-fsync °[pdmm0-sdi0 °[pdmm0-sdi1 °[pdmm0-sdi2 °[pdmm0-sdi3 °[pdmm0-clk-sleep °\pdmm0-sdi0-sleep °\pdmm0-sdi1-sleep °\pdmm0-sdi2-sleep °\pdmm0-sdi3-sleep °\pdmm0-fsync-sleep °\tsadcotp-pin ° [8otp-out ° [9uart0uart0-xfer ° [] uart0-cts ° [!uart0-rts ° ["uart0-rts-pin ° [uart1uart1-xfer °[]#uart1-cts °[$uart1-rts °[%uart1-rts-pin °[uart2-0uart2m0-xfer °[]uart2-1uart2m1-xfer °[]&spi0-0spi0m0-clk °]spi0m0-cs0 ° ]spi0m0-tx ° ]spi0m0-rx ° ]spi0m0-cs1 ° ]spi0-1spi0m1-clk °]spi0m1-cs0 °]spi0m1-tx °]spi0m1-rx °]spi0m1-cs1 °]spi0-2spi0m2-clk °].spi0m2-cs0 °]1spi0m2-tx °]/spi0m2-rx °]0i2s1i2s1-mclk °[i2s1-sclk °[i2s1-lrckrx °[i2s1-lrcktx °[i2s1-sdi °[i2s1-sdo °[i2s1-sdio1 °[i2s1-sdio2 °[i2s1-sdio3 °[i2s1-sleep� °\\\\\\\\\i2s2-0i2s2m0-mclk °[i2s2m0-sclk °[i2s2m0-lrckrx °[i2s2m0-lrcktx °[i2s2m0-sdi °[i2s2m0-sdo °[i2s2m0-sleep` °\\\\\\i2s2-1i2s2m1-mclk °[i2s2m1-sclk °[i2sm1-lrckrx °[i2s2m1-lrcktx °[i2s2m1-sdi °[i2s2m1-sdo °[i2s2m1-sleepP °\\\\\spdif-0spdifm0-tx °[spdif-1spdifm1-tx °[spdif-2spdifm2-tx °[sdmmc0-0sdmmc0m0-pwren °^sdmmc0m0-pin °^sdmmc0-1sdmmc0m1-pwren °^sdmmc0m1-pin °^fsdmmc0sdmmc0-clk °_Jsdmmc0-cmd °`Ksdmmc0-dectn °^Lsdmmc0-wrprt °^sdmmc0-bus1 °`sdmmc0-bus4@ °````Msdmmc0-pins€ °^^^^^^^^sdmmc0extsdmmc0ext-clk °asdmmc0ext-cmd °^sdmmc0ext-wrprt °^sdmmc0ext-dectn °^sdmmc0ext-bus1 °^sdmmc0ext-bus4@ °^^^^sdmmc0ext-pins€ °^^^^^^^^sdmmc1sdmmc1-clk ° _sdmmc1-cmd ° `sdmmc1-pwren °`sdmmc1-wrprt °`sdmmc1-dectn °`sdmmc1-bus1 °`sdmmc1-bus4@ °````sdmmc1-pins� ° ^ ^^^^^^^^emmcemmc-clk °bOemmc-cmd °cPemmc-pwren °[emmc-rstnout °[emmc-bus1 °cemmc-bus4@ °ccccemmc-bus8€ °ccccccccQpwm0pwm0-pin °[2pwm1pwm1-pin °[3pwm2pwm2-pin °[4pwmirpwmir-pin °[5gmac-1rgmiim1-pins` ° _ aa_aaa a a_ _aa___ _a____Trmiim1-pins °dbdddd d db b [ [[[[[gmac2phyfephyled-speed10 °[fephyled-duplex °[fephyled-rxm1 °[Wfephyled-txm1 °[fephyled-linkm1 °[Xtsadc_pintsadc-int ° [tsadc-pin ° [hdmi_pinhdmi-cec °[Bhdmi-hpd °eDcif-0dvp-d2d9-m0À °[[[[[ [ [ [[[[[cif-1dvp-d2d9-m1À °[[[[[[[[[[[[pmicpmic-int-l °]*usb2usb20-host-drv °]hirir-int °[msdmmciosdio-per-pin °egwifiwifi-en °[nwifi-host-wake °aobt-rst °[bt-en °[chosen ¾serial2:1500000n8external-gmac-clock fixed-clockMsY@ ]gmac_clkin@Rdc-12vregulator-fixeddc_12vYm)·A·isdmmc-regulatorregulator-fixed Î)œdefaultªfmvcc_sd)2Z A2Z  ÊNsdmmcio-regulatorregulator-gpio s)¶w@2Z  vcc_sdio Õvoltage)w@A2Z Y Ê+œdefaultªgvcc-host1-5v-regulatorregulator-fixed ä Î)œdefaultªh vcc_host1_5vY Ê+vcc-sysregulator-fixedvcc_sysYm)LK@ALK@ Êi+vcc-phy-regulatorregulator-fixedvcc_phyYmSleds gpio-ledsled-0 ÷firefly:blue:power ýheartbeat sj onµ#led-1 ÷firefly:yellow:user ýmmc1 sj offµadc-keys adc-keys !k -buttons >³ðbutton-recovery ÷Recovery Xh c'ir-receivergpio-ir-receiver sl }rc-khadasœdefaultªmsdio-pwrseqmmc-pwrseq-simpleœdefaultªno �p compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsvref-supplyinterrupt-namesmali-supply#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesmute-gpiosnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vnon-removablesnps,txpblclock_in_outphy-supplyphy-modesnps,aalsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ussnps,rxpbltx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplyregulator-typeenable-active-highlabellinux,default-triggerdefault-stateio-channelsio-channel-nameskeyup-threshold-microvoltlinux,codepress-threshold-microvoltlinux,rc-map-namereset-gpios