Ð þí8ôÐ(Oô˜%google,scarlet-rev15-sku0google,scarlet-rev15google,scarlet-rev14-sku0google,scarlet-rev14google,scarlet-rev13-sku0google,scarlet-rev13google,scarlet-rev12-sku0google,scarlet-rev12google,scarlet-rev11-sku0google,scarlet-rev11google,scarlet-rev10-sku0google,scarlet-rev10google,scarlet-rev9-sku0google,scarlet-rev9google,scarlet-rev8-sku0google,scarlet-rev8google,scarlet-rev7-sku0google,scarlet-rev7google,scarlet-rev6-sku0google,scarlet-rev6google,scarlet-rev5-sku0google,scarlet-rev5google,scarletgoogle,grurockchip,rk3399 +7tabletDGoogle ScarletaliasesJ/ethernet@fe300000T/i2c@ff3c0000Y/i2c@ff110000^/i2c@ff120000c/i2c@ff130000h/i2c@ff3d0000m/i2c@ff140000r/i2c@ff150000w/i2c@ff160000|/i2c@ff3e0000�/serial@ff180000‰/serial@ff190000‘/serial@ff1a0000™/serial@ff1b0000¡/serial@ff370000©/mmc@fe320000®/mmc@fe330000cpus+cpu-mapcluster0core0³core1³core2³core3³cluster1core0³core1³cpu@0·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@1·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@2·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@3·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@100·cpuarm,cortex-a72ÃÇpsciÕè ïþ´ ( <Gthermal-idleïO'[ôcpu@101·cpuarm,cortex-a72ÃÇpsciÕè ïþ´ ( <Gthermal-idleïO'[ôidle-stateskpscicpu-sleeparm,idle-statex‰ x[ú±„G cluster-sleeparm,idle-statex‰ �[ô±ÐG display-subsystemrockchip,display-subsystemÂmemory-controllerrockchip,rk3399-dmcÈÕè¨ädmc_clkðokay(÷  ( ;ðV@o'²Z€Š'²Z€§'²Z€Ä;šÊé 7P(/pmu_a53arm,cortex-a53-pmu=pmu_a72arm,cortex-a72-pmu=psci arm,psci-1.0Îsmctimerarm,armv8-timer@=   Hxin24m fixed-clock_n6oxin24m‚G“pcie@f8000000rockchip,rk3399-pcie Ãøý�axi-baseapb-base·pci+™ª¶ èÅÄG äaclkaclk-perfhclkpm0=123ÀsyslegacyclientÐ`ãñ , pcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-38‚úúà�ûàûà8‚ƒ„…†�€(%coremgmtmgmt-stickypipepmpclkaclkðokay 1:defaultHRbr‚interrupt-controller•™Gpcie@0,0Ã+wifi@0,0 qcom,ath10k(à ªGO_DUMOethernet@fe300000rockchip,rk3399-gmacÃþ0= Àmacirq8èighfjÕfMästmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macʉ %stmmacethØ å ðdisabledmmc@fe3100000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshcÃþ1@=@ððÑ€ èîMœ�äbiuciuciu-driveciu-sampleþÊy%reset ðdisabledmmc@fe3200000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshcÃþ2@=AððÑ€ Í ë èÎLš›äbiuciuciu-driveciu-sampleþÊz%resetðokay:defaultH!"#$%.8J [& do|‰–¤'°(mmc@fe330000+rockchip,rk3399-sdhci-5.1arasan,sdhci-5.1Ãþ3= ½  NðÑ€èNðäclk_xinclk_ahboemmc_cardclock‚)  phy_arasanÊÓðokay.äó G”usb@fe380000 generic-ehciÃþ8=èÈÉ*+ usb ðdisabledusb@fe3a0000 generic-ohciÃþ:=èÈÉ*+ usbðokay+bluetooth@1usbcf3,e300usb4ca,301aÃ:defaultH, &=Àwakeupusb@fe3c0000 generic-ehciÃþ<=èÊË-. usb ðdisabledusb@fe3e0000 generic-ohciÃþ>= èÊË-. usb ðdisableddebug@fe430000&arm,coresight-cpu-debugarm,primecellÃþCèM äapb_pclk³debug@fe432000&arm,coresight-cpu-debugarm,primecellÃþC èM äapb_pclk³debug@fe434000&arm,coresight-cpu-debugarm,primecellÃþC@èM äapb_pclk³debug@fe436000&arm,coresight-cpu-debugarm,primecellÃþC`èM äapb_pclk³debug@fe610000&arm,coresight-cpu-debugarm,primecellÃþaèL äapb_pclk³debug@fe710000&arm,coresight-cpu-debugarm,primecellÃþqèL äapb_pclk³usb@fe800000rockchip,rk3399-dwc3+0è�ƒöøôùGäref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk% %usb3-otgðokay/usb@fe800000 snps,dwc3Ãþ€=iè�öƒärefbus_earlysuspend"host01 usb2-phyusb3-phy *utmi_wide3Kl…¦Êðokayusb@fe900000rockchip,rk3399-dwc3+0è‚„÷øôùGäref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk& %usb3-otg ðdisabledusb@fe900000 snps,dwc3Ãþ�=nè‚÷„ärefbus_earlysuspend"otg23 usb2-phyusb3-phy *utmi_wide3Kl…¦Ê ðdisableddp@fec00000rockchip,rk3399-cdn-dpÃþÀ=  r¡õá ë èru¡oäcore-clkpclkspdifgrf4Ê HJý%spdifdptxapbcoreØ Èðokay/GÚportsport+endpoint@0ÃÙ5G¢endpoint@1ÃÙ6Gœinterrupt-controller@fee00000 arm,gic-v3™+•PÃþàþð ÿðÿñÿò= Ginterrupt-controller@fee20000arm,gic-v3-itséøÃþâGppi-partitionsinterrupt-partition-0Ginterrupt-partition-1Gsaradc@ff100000rockchip,rk3399-saradcÃÿ=> èPeäsaradcapb_pclkÔ %saradc-apb ðdisabledi2c@ff110000rockchip,rk3399-i2cÃÿ A ëÂèAU äi2cpclk=;:defaultH7+ ðdisabledi2c@ff120000rockchip,rk3399-i2cÃÿ B ëÂèBV äi2cpclk=#:defaultH8+ðokay_€26,digitizer@9 hid-over-i2cà  &=M:defaultH9:i2c@ff130000rockchip,rk3399-i2cÃÿ C ëÂèCW äi2cpclk=":defaultH;+ðokay_€26,touchscreen@10elan,ekth3500à &=:defaultH<= \ i2c@ff140000rockchip,rk3399-i2cÃÿ D ëÂèDX äi2cpclk=&:defaultH>+ ðdisabledi2c@ff150000rockchip,rk3399-i2cÃÿ E ëÂèEY äi2cpclk=%:defaultH?+ ðdisabledi2c@ff160000rockchip,rk3399-i2cÃÿ F ëÂèFZ äi2cpclk=$:defaultH@A+ðokay_€26,camera@36 ovti,ov5695Ã6:defaultHBè©äxvclkhCtD€ \EportendpointÙF�G¥camera@3c ovti,ov2685Ã<:defaultHGè©äxvclkhC€t \EportendpointÙH�G¦serial@ff180000&rockchip,rk3399-uartsnps,dw-apb-uartÃÿèQ`äbaudclkapb_pclk=c˜¢:defaultHI ðdisabledserial@ff190000&rockchip,rk3399-uartsnps,dw-apb-uartÃÿèRaäbaudclkapb_pclk=b˜¢:defaultHJ ðdisabledserial@ff1a0000&rockchip,rk3399-uartsnps,dw-apb-uartÃÿèSbäbaudclkapb_pclk=d˜¢:defaultHKðokayserial@ff1b0000&rockchip,rk3399-uartsnps,dw-apb-uartÃÿèTcäbaudclkapb_pclk=e˜¢:defaultHL ðdisabledspi@ff1c0000(rockchip,rk3399-spirockchip,rk3066-spiÃÿèG[äspiclkapb_pclk=D¯M M ´txrx:defaultHNOPQ+ ðdisabledspi@ff1d0000(rockchip,rk3399-spirockchip,rk3066-spiÃÿèH\äspiclkapb_pclk=5¯M M ´txrx:defaultsleepHRSTU+ðokay¾Vflash@0jedec,spi-norÃȘ–€spi@ff1e0000(rockchip,rk3399-spirockchip,rk3066-spiÃÿèI]äspiclkapb_pclk=4¯MM´txrx:defaultHWXYZ+ðokaycr50@0 google,cr50à &=:defaultH[È 5spi@ff1f0000(rockchip,rk3399-spirockchip,rk3066-spiÃÿèJ^äspiclkapb_pclk=C¯MM´txrx:defaultH\]^_+ ðdisabledspi@ff200000(rockchip,rk3399-spirockchip,rk3066-spiÃÿ èK_äspiclkapb_pclk=„¯`` ´txrx:defaultHabcdÊ+ðokayec@0google,cros-ec-spià &=:defaultHeÈ-ÆÀi2c-tunnelgoogle,cros-ec-i2c-tunnelÚ+sbs-battery@bsbs,sbs-batteryà ìextcon0google,extcon-usbc-cros-ecG/keyboard-controllergoogle,cros-ec-keyb(8 KDe;<=>?@A B CD}0Y1 d"#(  \V |})  Ž + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ithermal-zonescpu-thermalrdˆè–ftripscpu_alert0¦Ð²Ð?passiveGgcpu_alert1¦X²Ð?passiveGhcpu_crit¦s²Ð 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:syscon@ff320000)rockchip,rk3399-pmugrfsysconsimple-mfdÃÿ2Gio-domains&rockchip,rk3399-pmu-io-voltage-domainðokay Uspi@ff350000(rockchip,rk3399-spirockchip,rk3066-spiÃÿ5è‚‚äspiclkapb_pclk=<:defaultHƒ„…†+ ðdisabledserial@ff370000&rockchip,rk3399-uartsnps,dw-apb-uartÃÿ7è‚‚"äbaudclkapb_pclk=f˜¢:defaultH‡ ðdisabledi2c@ff3c0000rockchip,rk3399-i2cÃÿ< ‚  ëÂè‚ ‚ äi2cpclk=9:defaultHˆ+ ðdisabledi2c@ff3d0000rockchip,rk3399-i2cÃÿ= ‚  ëÂè‚ ‚ äi2cpclk=8:defaultH‰+ ðdisabledi2c@ff3e0000rockchip,rk3399-i2cÃÿ> ‚  ëÂè‚ ‚ äi2cpclk=::defaultHŠ+ðokay_€26,da7219@1a dlg,da7219à &=èYämclk d ( tdiff:defaultH‹ ‡ ’Œ  GÙda7219_aad ­ ¾ Ê2 Öô æ ÷32ms_64ms    * :! J>pwm@ff420000(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB \:defaultH�è‚ðokayGÏpwm@ff420010(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB \:defaultHŽè‚ðokayGäpwm@ff420020(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB  \:defaultH�è‚ðokayGÍpwm@ff420030(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB0 \:defaultH�è‚ðokayGËdfi@ff630000Ãÿc@rockchip,rk3399-dfiÈ=ƒèy äpclk_ddr_monðokayGvideo-codec@ff650000rockchip,rk3399-vpuÃÿe =rq Àvepuvdpuèëê äaclkhclk g‘Êiommu@ff650800rockchip,iommuÃÿe@=sèëê äaclkiface nÊG‘video-codec@ff660000rockchip,rk3399-vdecÃÿf=t èí쟞äaxiahbcabaccore g’Ê iommu@ff660480rockchip,iommu Ãÿf€@ÿfÀ@=uèíì äaclkifaceÊ  nG’iommu@ff670800rockchip,iommuÃÿg@=*èáÝ äaclkiface n ðdisabledrga@ff680000rockchip,rk3399-rgaÃÿh=7èÜåmäaclkhclksclkjgi %coreaxiahbÊ!efuse@ff690000rockchip,rk3399-efuseÃÿi€+è} äpclk_efusecpu-id@7Ãcpu-leakage@17Ãgpu-leakage@18Ãcenter-leakage@19Ãcpu-leakage@1aÃlogic-leakage@1bÃwafer-info@1cÃdma-controller@ff6d0000arm,pl330arm,primecellÃÿm@ = { †èÓ äapb_pclkG`dma-controller@ff6e0000arm,pl330arm,primecellÃÿn@ = { †èÔ äapb_pclkGMclock-controller@ff750000rockchip,rk3399-pmucruÃÿuè“äxin24mØ‚ � ‚(JñG‚clock-controller@ff760000rockchip,rk3399-cruÃÿvè“äxin24mØ ‚ �ˆ ÀÀ@ÂÁBÉÂCãxÞíD#ÃF_^;šÊðÑ€xhÀ<4`õáõáúð€/¯õáúð€ׄ ë ëÂׄׄGsyscon@ff770000&rockchip,rk3399-grfsysconsimple-mfdÃÿw+G io-domains"rockchip,rk3399-io-voltage-domainðokay ª · Ä Ô(mipi-dphy-rx0rockchip,rk3399-mipi-dphy-rx0èw¥oädphy-refdphy-cfggrfÊ áðokayG¤usb2phy@e450rockchip,rk3399-usb2phyÃäPè{äphyclk‚oclk_usbphy0_480mðokayG*host-port á= ÀlinestateðokayG+otg-port á0=ghjÀotg-bvalidotg-idlinestateðokayG0usb2phy@e460rockchip,rk3399-usb2phyÃä`è|äphyclk‚oclk_usbphy1_480m ðdisabledG-host-port á= ÀlinestateðokayG.otg-port á0=lmoÀotg-bvalidotg-idlinestateðokayG2phy@f780rockchip,rk3399-emmc-phyÃ÷€$è”äemmcclk ì2 áðokayG)pcie-phyrockchip,rk3399-pcie-phyèŠärefclk á‡%phyðokayGphy@ff7c0000rockchip,rk3399-typec-phyÃÿ|è~}ätcpdcoretcpdphy-ref ~úð€Ê•”L%uphyuphy-pipeuphy-tcphyØ ðokay/dp-port áG4usb3-port áG1phy@ff800000rockchip,rk3399-typec-phyÃÿ€è€ätcpdcoretcpdphy-ref €úð€Ê �œM%uphyuphy-pipeuphy-tcphyØ  ðdisableddp-port áusb3-port áG3watchdog@ff848000 rockchip,rk3399-wdtsnps,dw-wdtÃÿ„€è|=xrktimer@ff850000rockchip,rk3399-timerÃÿ…=QèhZ äpclktimerspdif@ff870000rockchip,rk3399-spdifÃÿ‡=B¯`´tx ämclkhclkèU×ÊÈðokayGÖi2s@ff880000(rockchip,rk3399-i2srockchip,rk3066-i2sÃÿˆØ ='¯``´txrxäi2s_clki2s_hclkèVÔ:defaultH•ÊÈðokayGÕi2s@ff890000(rockchip,rk3399-i2srockchip,rk3066-i2sÃÿ‰=(¯``´txrxäi2s_clki2s_hclkèWÕ:defaultH–ÊÈ ðdisabledi2s@ff8a0000(rockchip,rk3399-i2srockchip,rk3066-i2sÃÿŠ=)¯``´txrxäi2s_clki2s_hclkèXÖÊÈ ðdisabledG©vop@ff8f0000rockchip,rk3399-vop-litÃÿ�>ü=w ÛÛׄõáèÛµÛäaclk_vopdclk_vophclk_vop g—Ê %axiahbdclkðokayport+Gendpoint@0ÃÙ˜G®endpoint@1ÃÙ™G¼endpoint@2ÃÙšG¬endpoint@3ÃÙ›G¸endpoint@4ÃÙœG6iommu@ff8f3f00rockchip,iommuÃÿ�?=wèÛÛ äaclkifaceÊ nðokayG—vop@ff900000rockchip,rk3399-vop-bigÃÿ�>ü=v ÙÙׄõáèÙ´Ùäaclk_vopdclk_vophclk_vop g�Ê %axiahbdclkðokayport+Gendpoint@0ÃÙžG»endpoint@1ÃÙŸG­endpoint@2ÃÙ G«endpoint@3ÃÙ¡G·endpoint@4ÃÙ¢G5iommu@ff903f00rockchip,iommuÃÿ�?=vèÙÙ äaclkifaceÊ nðokayG�isp0@ff910000rockchip,rk3399-cif-ispÃÿ‘@=+ènéãäispaclkhclk g£¤ dphyÊðokayports+port@0Ã+endpoint@0ÃÙ¥�GFendpoint@1ÃÙ¦�GHiommu@ff914000rockchip,iommu Ãÿ‘@ÿ‘P=+èéã äaclkiface nÊ ðokayG£isp1@ff920000rockchip,rk3399-cif-ispÃÿ’@=,èoêääispaclkhclk g§¨ dphyÊ ðdisabledports+port@0Ã+iommu@ff924000rockchip,iommu Ãÿ’@ÿ’P=,èêä äaclkiface nÊ G§hdmi-soundsimple-audio-card i2s 4 Nhdmi-sound ðdisabledsimple-audio-card,cpu e©simple-audio-card,codec eªhdmi@ff940000rockchip,rk3399-dw-hdmiÃÿ”=(ètqpoäiahbisfrcecgrfrefÊ¢Ø È ðdisabledGªportsport+endpoint@0ÃÙ«G endpoint@1ÃÙ¬Gšmipi@ff960000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsiÃÿ–€=- è¢p£oärefpclkphy_cfggrfÊû%apbØ +ðokay oports+port@0Ã+endpoint@0ÃÙ­GŸendpoint@1ÃÙ®G˜port@1ÃendpointÙ¯Gµpanel@0à |° †±:defaultH²innolux,p097pfgh³ “´ports+port@0ÃendpointÙµG¯port@1Ãendpoint@1Ù¶G¹mipi@ff968000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsiÃÿ–€€=. è¢q¤oärefpclkphy_cfggrfÊü%apbØ + áðokayG¨ports+port@0Ã+endpoint@0ÃÙ·G¡endpoint@1ÃÙ¸G›port@1ÃendpointÙ¹G¶edp@ff970000rockchip,rk3399-edpÃÿ—€= èjlo ädppclkgrf:defaultHºÊ%dpØ  ðdisabledports+port@0Ã+endpoint@0ÃÙ»Gžendpoint@1ÃÙ¼G™gpu@ff9a0000#rockchip,rk3399-maliarm,mali-t860Ãÿš0= ÀjobmmugpuèÐïÊ#ðokay(½ Ÿ¾Gjpinctrlrockchip,rk3399-pinctrlØ È+:default H¿ÀÁgpio@ff720000rockchip,gpio-bankÃÿrè‚= « »•™â ÇCLK_32K_APEC_IN_RW_ODSPK_PA_ENWLAN_PERST_1V8_LWLAN_PD_1V8_LWLAN_RF_KILL_1V8_LBIGCPU_DVS_PWMSD_CD_L_JTAG_ENBT_EN_BT_RF_KILL_1V8_LPMUIO2_33_18_L_PP3300_S0_ENTOUCH_RESET_LAP_EC_WARM_RESET_REQPEN_RESET_LAP_FLASH_WP_LGgpio@ff730000rockchip,gpio-bankÃÿsè‚= « »•™‰ ÇPEN_INT_ODLPEN_EJECT_ODLBT_HOST_WAKE_1V8_LWLAN_HOST_WAKE_1V8_LTOUCH_INT_ODLAP_EC_S3_S0_LAP_EC_OVERTEMPAP_SPI_FLASH_MISOAP_SPI_FLASH_MOSI_RAP_SPI_FLASH_CLK_RAP_SPI_FLASH_CS_L_RSD_CARD_DET_ODLAP_EXPANSION_IO1AP_EXPANSION_IO2AP_I2C_DISP_SDAAP_I2C_DISP_SCLH1_INT_ODLEC_AP_INT_ODLLITCPU_DVS_PWMAP_I2C_AUDIO_SDAAP_I2C_AUDIO_SCLAP_EXPANSION_IO3HEADSET_INT_ODLAP_EXPANSION_IO4G&gpio@ff780000rockchip,gpio-bankÃÿxèP= « »•™  ÇAP_I2C_PEN_SDAAP_I2C_PEN_SCLSD_IO_PWR_ENUCAM_RST_LPP1250_CAM_ENWCAM_RST_LAP_EXPANSION_IO5AP_I2C_CAM_SDAAP_I2C_CAM_SCLAP_H1_SPI_MISOAP_H1_SPI_MOSIAP_H1_SPI_CLKAP_H1_SPI_CS_LUART_EXPANSION_TX_AP_RXUART_AP_TX_EXPANSION_RXUART_EXPANSION_RTS_AP_CTSUART_AP_RTS_EXPANSION_CTSAP_SPI_EC_MISOAP_SPI_EC_MOSIAP_SPI_EC_CLKAP_SPI_EC_CS_LPP2800_CAM_ENCLK_24M_CAMWLAN_PCIE_CLKREQ_1V8_LSD_PWR_3000_1800_LGEgpio@ff788000rockchip,gpio-bankÃÿx€èQ= « »•™‚ ÇI2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDI_0STRAP_LCDBIAS_LSTRAP_FEATURE_1STRAP_FEATURE_2I2S0_SDO_0gpio@ff790000rockchip,gpio-bankÃÿyèR= « »•™Ü ÇI2S_MCLKAP_I2C_EXPANSION_SDAAP_I2C_EXPANSION_SCLDMIC_ENAP_I2C_TS_SDAAP_I2C_TS_SCLGPU_DVS_PWMUART_DBG_TX_AP_RXUART_AP_TX_DBG_RXBL_ENBL_PWMDISPLAY_RST_LPPVARP_LCD_ENPPVARN_LCD_ENSD_SLOT_PWR_ENG±pcfg-pull-up ×GÆpcfg-pull-down äGÈpcfg-pull-none óGÂpcfg-pull-none-12ma ó GÄpcfg-pull-none-13ma ó GÃpcfg-pull-none-18ma ó pcfg-pull-none-20ma ó pcfg-pull-up-2ma × pcfg-pull-up-8ma × pcfg-pull-up-18ma × pcfg-pull-up-20ma × pcfg-pull-down-4ma ä pcfg-pull-down-8ma ä pcfg-pull-down-12ma ä pcfg-pull-down-18ma ä pcfg-pull-down-20ma ä pcfg-output-high GÉpcfg-output-low pcfg-input-enable &pcfg-input-pull-up & × pcfg-input-pull-down & ä clockclk-32k 3ÂGÀcifcif-clkin 3 Âcif-clkouta 3 Âedpedp-hpd 3ÂGºgmacrgmii-pinsð 3à à  ÂÂÂÂÃÃÂÂÃÃrmii-pins  3  à   ÂÂÂÂÃÃi2c0i2c0-xfer 3ÂÂGˆi2c1i2c1-xfer 3ÂÂG7i2c2i2c2-xfer 3ÄÄG8i2c3i2c3-xfer 3ÂÂG;i2c4i2c4-xfer 3  ÂG‰i2c5i2c5-xfer 3  ÂG>i2c6i2c6-xfer 3  ÂG?i2c7i2c7-xfer 3ÂÂG@i2c8i2c8-xfer 3ÂÂGŠi2s0i2s0-2ch-bus` 3ÂÂÂÂÂÂi2s0-8ch-bus` 3ÅÅÅÅÅÅG•i2s1i2s1-2ch-busP 3ÂÂÂÂÂG–sdio0sdio0-bus1 3Æsdio0-bus4@ 3ÆÆÆÆsdio0-cmd 3Æsdio0-clk 3Âsdio0-cd 3Æsdio0-pwr 3Æsdio0-bkpwr 3Æsdio0-wp 3Æsdio0-int 3Æsdmmcsdmmc-bus1 3Æsdmmc-bus4@ 3Ç Ç Ç ÇG%sdmmc-clk 3 ÇG!sdmmc-cmd 3 ÇG"sdmmc-cd 3ÂG#sdmmc-wp 3Æsdmmc-cd-pin 3 ÆG$suspendap-pwroff 3ÂG¿ddrio-pwroff 3Âspdifspdif-bus 3Âspdif-bus-1 3Âspi0spi0-clk 3ÆGNspi0-cs0 3ÆGQspi0-cs1 3Æspi0-tx 3ÆGOspi0-rx 3ÆGPspi1spi1-clk 3 ÆGRspi1-cs0 3 ÆGUspi1-rx 3ÆGTspi1-tx 3ÆGSspi1-sleep@ 3 È ÈÈÈGVspi2spi2-clk 3 ÆGWspi2-cs0 3 ÆGZspi2-rx 3 ÆGYspi2-tx 3 ÆGXspi3spi3-clk 3ÆGƒspi3-cs0 3ÆG†spi3-rx 3ÆG…spi3-tx 3ÆG„spi4spi4-clk 3ÆG\spi4-cs0 3ÆG_spi4-rx 3ÆG^spi4-tx 3ÆG]spi5spi5-clk 3ÆGaspi5-cs0 3ÆGdspi5-rx 3ÆGcspi5-tx 3ÆGbtestclktest-clkout0 3Âtest-clkout1 3ÂGAtest-clkout2 3Âtsadcotp-pin 3ÂGkotp-out 3ÂGluart0uart0-xfer 3ÆÂGIuart0-cts 3Âuart0-rts 3Âuart1uart1-xfer 3 Æ ÂGJuart2auart2a-xfer 3Æ Âuart2buart2b-xfer 3ÆÂuart2cuart2c-xfer 3ÆÂGKuart3uart3-xfer 3ÆÂGLuart3-cts 3Âuart3-rts 3Âuart4uart4-xfer 3ÆÂG‡uarthdcpuarthdcp-xfer 3ÆÂpwm0pwm0-pin 3ÂG�pwm0-pin-pull-down 3Èvop0-pwm-pin 3Âvop1-pwm-pin 3Âpwm1pwm1-pin 3ÂGŽpwm1-pin-pull-down 3Èpwm2pwm2-pin 3ÂG�pwm2-pin-pull-down 3Èpwm3apwm3a-pin 3ÂG�pwm3bpwm3b-pin 3Âhdmihdmi-i2c-xfer 3ÂÂhdmi-cec 3Âpciepci-clkreqn-cpm 3ÂGpci-clkreqnb-cpm 3Âpcfg-pull-none-8ma ó GÇbacklight-enablebl-en 3ÂGãcros-ecec-ap-int-l 3ÆGediscrete-regulatorssd-io-pwr-en 3ÂGÒsd-pwr-1800-sel 3ÆGÓsd-slot-pwr-en 3ÂGÑdisplay-rst-l 3ÈG²ppvarp-lcd-en 3ÂGÞppvarn-lcd-en 3ÂGÝcodecheadset-int-l 3ÆG‹mic-int 3 Èmax98357asdmode-en 3ÈGÔtouchscreentouch-int-l 3ÈG<touch-reset-l 3 ÈG=trackpadap-i2c-tp-pu-en 3 Étrackpad-int-l 3Æwifiwlan-module-reset-l 3 Âbt-host-wake-l 3ÂG,bt-en-1v8-l 3ÂGàwlan-pd-1v8-l 3ÂGáwlan-rf-kill-1v8-l 3ÆGÁwifi-perst-l 3ÂGwlan-host-wake-l 3Æwrite-protectap-fw-wp 3 Âpcfg-pull-none-6ma ó GÅcamerapp1250-dvdd 3ÂGÛpp2800-avdd 3ÂGßucam_rst 3ÂGGwcam_rst 3ÂGBdigitizerpen-int-odl 3ÆG9pen-reset-l 3 ÂG:dmicdmic-en 3ÂGåpenpen-eject-odl 3ÆGætpmh1-int-od-l 3ÆG[opp-table-0operating-points-v2 AG opp00 LQ– S 5 aœ@opp01 L#ÃF S –¨opp02 L0£, S øPopp03 L<Ü S » opp04 LG†Œ Sà˜opp05 LTfr SÈà ropp06 LZJ SŒ0opp-table-1operating-points-v2 AG opp00 LQ– S 5 aœ@opp01 L#ÃF S 5opp02 L0£, S –¨opp03 L<Ü S øPopp04 LG†Œ S » opp05 LTfr Sà˜opp06 L_Ø" S� ropp07 LkIÒ SŒ0opp08 Lx)¸ SÐopp-table-2operating-points-v2G½opp00 L ë S 5opp01 L³Ü@ S 5opp02 Lׄ S –¨opp03 LÍe S øPopp04 L#ÃF SHopp05 L/¯ Sg8dmc_opp_tableoperating-points-v2Gopp00 Lׄ S » opp01 L'²Z€ S » opp02 L/¯ S » opp03 L7P( S »  rchosen ~serial2:115200n8ppvar-sysregulator-fixed Šppvar_sys ™ ­GÊpp1200-lpddrregulator-fixed Špp1200_lpddr ™ ­ ¿O€ ×O€ ïÊpp1800regulator-fixed Špp1800 ™ ­ ¿w@ ×w@ ïÊGpp3300regulator-fixed Špp3300 ™ ­ ¿2Z  ×2Z  ïÊGŒpp5000regulator-fixed Špp5000 ™ ­ ¿LK@ ×LK@ ïÊppvar-bigcpu-pwmpwm-regulator Šppvar_bigcpu_pwm úË  ÿÊ d d ™ ­ ¿ 5J ×ÓGÌppvar-bigcpuvctrl-regulator Šppvar_bigcpu ¿ 5J ×Ó 1Ì = 5JÓ PBGppvar-litcpu-pwmpwm-regulator Šppvar_litcpu_pwm úÍ  ÿÊ d d ™ ­ ¿ =J ×NGÎppvar-litcpuvctrl-regulator Šppvar_litcpu ¿ =J ×N 1Î = =JN P€G ppvar-gpu-pwmpwm-regulator Šppvar_gpu_pwm úÏ  ÿÊ d d ™ ­ ¿ 3p ×ÇPGÐppvar-gpuvctrl-regulator Šppvar_gpu ¿ 3p ×ÇP 1Ð = 3pÇP P†G¾pp900-appp3000-sd-slotregulator-fixed Špp3000_sd_slot:defaultHÑ n �± ïŒG'ppvar-sd-card-ioregulator-gpio Šppvar_sd_card_io:defaultHÒÓ n †E 4E!w@2Z  ¿w@ ×2Z G(pp3300-trackpadap-rtc-clk fixed-clock_€oxin32k‚max98357amaxim,max98357a:defaultHÔ ’ ŸÈðokayG×soundrockchip,rk3399-gru-sound ¬ÕÖ ¹×ØÙÚpp1250-s3regulator-fixed Špp1250_s3 ™ ­ ¿Ð ×Ð ïÊGÜpp1250-dvddregulator-fixed Špp1250_dvdd:defaultHÛ n �E Èè ïÜGDpp900-s0regulator-fixed Špp900_s0 ™ ­ ¿ »  × »  ïÊGppvarn-lcdregulator-fixed Šppvarn_lcd:defaultHÝ n �± ïÊG´ppvarp-lcdregulator-fixed Šppvarp_lcd:defaultHÞ n �± ïÊG³pp900-s3regulator-fixed Špp900_s3 ™ ­ ¿ »  × »  ïpp2800-avddregulator-fixed Špp2800_avdd:defaultHß n �E Èd ïŒGCbt-3v3regulator-fixed Šbt_3v3:defaultHà n � ïŒGâwlan-3v3regulator-fixed Šwlan_3v3:defaultHá n � Ù' ïâGbacklightpwm-backlight †±:defaultHã úäB@ õ'G°dmic dmic-codec ±:defaultHåúGØgpio-keys gpio-keys:defaultHæpen-insert Pen Insert 4&%0A compatibleinterrupt-parent#address-cells#size-cellschassis-typemodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4mmc0mmc1cpudevice_typeregenable-methodcapacity-dmips-mhzclocks#cooling-cellsdynamic-power-coefficientcpu-idle-statesoperating-points-v2cpu-supplyphandleduration-usexit-latency-usentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usmin-residency-usportsrockchip,pmudevfreq-eventsclock-namesstatusrockchip,pd-idle-nsrockchip,sr-idle-nsrockchip,sr-mc-gate-idle-nsrockchip,srpd-lite-idle-nsrockchip,standby-idle-nsrockchip,ddr3_odt_dis_freqrockchip,lpddr3_odt_dis_freqrockchip,lpddr4_odt_dis_freqrockchip,sr-mc-gate-idle-dis-freq-hzrockchip,srpd-lite-idle-dis-freq-hzrockchip,standby-idle-dis-freq-hzcenter-supplyinterruptsarm,no-tick-in-suspendclock-frequencyclock-output-names#clock-cellsreg-names#interrupt-cellsaspm-no-l0sbus-rangeinterrupt-namesinterrupt-map-maskinterrupt-mapmax-link-speedmsi-mapphysphy-namesrangesresetsreset-namesep-gpiospinctrl-namespinctrl-0vpcie3v3-supplyvpcie1v8-supplyvpcie0v9-supplypcie-reset-suspendinterrupt-controllerqcom,ath10k-calibration-variantpower-domainsrockchip,grfsnps,txpblmax-frequencyfifo-depthassigned-clocksassigned-clock-ratesbus-widthcap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplyarasan,soc-ctl-syscondisable-cqe-dcmdmmc-hs400-1_8vmmc-hs400-enhanced-strobenon-removableextcondr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirk#sound-dai-cellsremote-endpointmsi-controller#msi-cellsaffinity#io-channel-cellsi2c-scl-falling-time-nsi2c-scl-rising-time-nshid-descr-addrreset-gpiosavdd-supplydvdd-supplydovdd-supplydata-lanesreg-shiftreg-io-widthdmasdma-namespinctrl-1spi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countgoogle,usb-port-idkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymappolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#power-domain-cellspm_qospmu1830-supplydlg,micbias-lvldlg,mic-amp-in-selVDD-supplyVDDMIC-supplyVDDIO-supplydlg,adc-1bit-rptdlg,btn-avgdlg,btn-cfgdlg,mic-det-thrdlg,jack-ins-debdlg,jack-det-ratedlg,jack-rem-debdlg,a-d-btn-thrdlg,d-b-btn-thrdlg,b-c-btn-thrdlg,c-mic-btn-thr#pwm-cellsiommus#iommu-cells#dma-cellsarm,pl330-periph-burst#reset-cellsaudio-supplybt656-supplygpio1830-supplysdmmc-supply#phy-cellsdrive-impedance-ohmrockchip,disable-mmu-resetsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namesound-daiclock-masterbacklightenable-gpiosavee-supplymali-supplygpio-controller#gpio-cellsgpio-line-namesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplypwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitctrl-supplyctrl-voltage-rangeregulator-settling-time-up-usenable-active-highgpioenable-gpiosdmode-gpiossdmode-delayrockchip,cpurockchip,codecstartup-delay-usregulator-enable-ramp-delaypwm-delay-usdmicen-gpioswakeup-delay-mslabellinux,codelinux,input-typewakeup-source