Ð þí¼8ôŒ(0ôTgoogle,scarlet-rev15-sku7google,scarlet-rev15google,scarlet-rev14-sku7google,scarlet-rev14google,scarlet-rev13-sku7google,scarlet-rev13google,scarlet-rev12-sku7google,scarlet-rev12google,scarlet-rev11-sku7google,scarlet-rev11google,scarlet-rev10-sku7google,scarlet-rev10google,scarlet-rev9-sku7google,scarlet-rev9google,scarlet-rev8-sku7google,scarlet-rev8google,scarlet-rev7-sku7google,scarlet-rev7google,scarlet-rev6-sku7google,scarlet-rev6google,scarlet-rev5-sku7google,scarlet-rev5google,scarlet-rev4-sku7google,scarlet-rev4google,scarlet-rev3-sku7google,scarlet-rev3google,scarletgoogle,grurockchip,rk3399 +7tabletDGoogle ScarletaliasesJ/ethernet@fe300000T/i2c@ff3c0000Y/i2c@ff110000^/i2c@ff120000c/i2c@ff130000h/i2c@ff3d0000m/i2c@ff140000r/i2c@ff150000w/i2c@ff160000|/i2c@ff3e0000�/serial@ff180000‰/serial@ff190000‘/serial@ff1a0000™/serial@ff1b0000¡/serial@ff370000©/mmc@fe320000®/mmc@fe330000cpus+cpu-mapcluster0core0³core1³core2³core3³cluster1core0³core1³cpu@0·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@1·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@2·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@3·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@100·cpuarm,cortex-a72ÃÇpsciÕè ïþ´ ( <Gthermal-idleïO'[ôcpu@101·cpuarm,cortex-a72ÃÇpsciÕè ïþ´ ( <Gthermal-idleïO'[ôidle-stateskpscicpu-sleeparm,idle-statex‰ x[ú±„G cluster-sleeparm,idle-statex‰ �[ô±ÐG display-subsystemrockchip,display-subsystemÂmemory-controllerrockchip,rk3399-dmcÈÕè¨ädmc_clkðokay(÷  ( ;ðV@o'²Z€Š'²Z€§'²Z€Ä;šÊé 7P(/pmu_a53arm,cortex-a53-pmu=pmu_a72arm,cortex-a72-pmu=psci arm,psci-1.0Îsmctimerarm,armv8-timer@=   Hxin24m fixed-clock_n6oxin24m‚G“pcie@f8000000rockchip,rk3399-pcie Ãøý�axi-baseapb-base·pci+™ª¶ èÅÄG äaclkaclk-perfhclkpm0=123ÀsyslegacyclientÐ`ãñ , pcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-38‚úúà�ûàûà8‚ƒ„…†�€(%coremgmtmgmt-stickypipepmpclkaclkðokay 1:defaultHRbr‚interrupt-controller•™Gpcie@0,0Ã+ethernet@fe300000rockchip,rk3399-gmacÃþ0= Àmacirq8èighfjÕfMästmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macª‰ %stmmaceth¸ Å ðdisabledmmc@fe3100000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshcÃþ1@=@ÐðÑ€ èîMœ�äbiuciuciu-driveciu-sampleÞªy%reset ðdisabledmmc@fe3200000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshcÃþ2@=AÐðÑ€éÍù ë èÎLš›äbiuciuciu-driveciu-sampleÞªz%resetðokay:defaultH!"#$%* ;& DO\iv„'�(mmc@fe330000+rockchip,rk3399-sdhci-5.1arasan,sdhci-5.1Ãþ3= � éNùðÑ€èNðäclk_xinclk_ahboemmc_cardclock‚)  phy_arasanª³ðokayÄÓíG”usb@fe380000 generic-ehciÃþ8=èÈÉ*+ usb ðdisabledusb@fe3a0000 generic-ohciÃþ:=èÈÉ*+ usbðokay+bluetooth@1usbcf3,e300usb4ca,301aÃ:defaultH, &=Àwakeupusb@fe3c0000 generic-ehciÃþ<=èÊË-. usb ðdisabledusb@fe3e0000 generic-ohciÃþ>= èÊË-. usb ðdisableddebug@fe430000&arm,coresight-cpu-debugarm,primecellÃþCèM äapb_pclk³debug@fe432000&arm,coresight-cpu-debugarm,primecellÃþC èM äapb_pclk³debug@fe434000&arm,coresight-cpu-debugarm,primecellÃþC@èM äapb_pclk³debug@fe436000&arm,coresight-cpu-debugarm,primecellÃþC`èM äapb_pclk³debug@fe610000&arm,coresight-cpu-debugarm,primecellÃþaèL äapb_pclk³debug@fe710000&arm,coresight-cpu-debugarm,primecellÃþqèL äapb_pclk³usb@fe800000rockchip,rk3399-dwc3+0è�ƒöøôùGäref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk% %usb3-otgðokayû/usb@fe800000 snps,dwc3Ãþ€=iè�öƒärefbus_earlysuspendhost01 usb2-phyusb3-phy  utmi_wide+Le†ªðokayusb@fe900000rockchip,rk3399-dwc3+0è‚„÷øôùGäref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk& %usb3-otg ðdisabledusb@fe900000 snps,dwc3Ãþ�=nè‚÷„ärefbus_earlysuspendotg23 usb2-phyusb3-phy  utmi_wide+Le†ª ðdisableddp@fec00000rockchip,rk3399-cdn-dpÃþÀ= ér¡ùõá ë èru¡oäcore-clkpclkspdifgrf4ª HJý%spdifdptxapbcore¸ ¨ðokayû/GØportsport+endpoint@0ù5G¢endpoint@1ù6Gœinterrupt-controller@fee00000 arm,gic-v3™+•PÃþàþð ÿðÿñÿò= Ginterrupt-controller@fee20000arm,gic-v3-itsÉØÃþâGppi-partitionsinterrupt-partition-0ãGinterrupt-partition-1ãGsaradc@ff100000rockchip,rk3399-saradcÃÿ=>ìèPeäsaradcapb_pclkÔ %saradc-apb ðdisabledi2c@ff110000rockchip,rk3399-i2cÃÿéAù ëÂèAU äi2cpclk=;:defaultH7+ ðdisabledi2c@ff120000rockchip,rk3399-i2cÃÿéBù ëÂèBV äi2cpclk=#:defaultH8+ðokay_€þ2,digitizer@9 hid-over-i2cà  &=-:defaultH9:i2c@ff130000rockchip,rk3399-i2cÃÿéCù ëÂèCW äi2cpclk=":defaultH;+ðokay_€þ2,touchscreen@10elan,ekth3500à &=:defaultH<= < i2c@ff140000rockchip,rk3399-i2cÃÿéDù ëÂèDX äi2cpclk=&:defaultH>+ ðdisabledi2c@ff150000rockchip,rk3399-i2cÃÿéEù ëÂèEY äi2cpclk=%:defaultH?+ ðdisabledi2c@ff160000rockchip,rk3399-i2cÃÿéFù ëÂèFZ äi2cpclk=$:defaultH@A+ðokay_€þ2,camera@36 ovti,ov5695Ã6:defaultHBè©äxvclkHCTD` <Eportendpoint¹FmG¥camera@3c ovti,ov2685Ã<:defaultHGè©äxvclkHC`T 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*>pwm@ff420000(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB <:defaultH�è‚ðokayGÍpwm@ff420010(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB <:defaultHŽè‚ðokayGâpwm@ff420020(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB  <:defaultH�è‚ðokayGËpwm@ff420030(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB0 <:defaultH�è‚ðokayGÉdfi@ff630000Ãÿc@rockchip,rk3399-dfiÈ=ƒèy äpclk_ddr_monðokayGvideo-codec@ff650000rockchip,rk3399-vpuÃÿe =rq Àvepuvdpuèëê äaclkhclk G‘ªiommu@ff650800rockchip,iommuÃÿe@=sèëê äaclkiface NªG‘video-codec@ff660000rockchip,rk3399-vdecÃÿf=t èí쟞äaxiahbcabaccore G’ª iommu@ff660480rockchip,iommu Ãÿf€@ÿfÀ@=uèíì äaclkifaceª  NG’iommu@ff670800rockchip,iommuÃÿg@=*èáÝ äaclkiface N ðdisabledrga@ff680000rockchip,rk3399-rgaÃÿh=7èÜåmäaclkhclksclkjgi %coreaxiahbª!efuse@ff690000rockchip,rk3399-efuseÃÿi€+è} äpclk_efusecpu-id@7Ãcpu-leakage@17Ãgpu-leakage@18Ãcenter-leakage@19Ãcpu-leakage@1aÃlogic-leakage@1bÃwafer-info@1cÃdma-controller@ff6d0000arm,pl330arm,primecellÃÿm@ = [ fèÓ äapb_pclkG`dma-controller@ff6e0000arm,pl330arm,primecellÃÿn@ = [ fèÔ äapb_pclkGMclock-controller@ff750000rockchip,rk3399-pmucruÃÿuè“äxin24m¸‚ }é‚ù(JñG‚clock-controller@ff760000rockchip,rk3399-cruÃÿvè“äxin24m¸ ‚ }ˆéÀÀ@ÂÁBÉÂCãxÞíDù#ÃF_^;šÊðÑ€xhÀ<4`õáõáúð€/¯õáúð€ׄ ë ëÂׄׄGsyscon@ff770000&rockchip,rk3399-grfsysconsimple-mfdÃÿw+G io-domains"rockchip,rk3399-io-voltage-domainðokay Š — ¤ ´(mipi-dphy-rx0rockchip,rk3399-mipi-dphy-rx0èw¥oädphy-refdphy-cfggrfª ÁðokayG¤usb2phy@e450rockchip,rk3399-usb2phyÃäPè{äphyclk‚oclk_usbphy0_480mðokayG*host-port Á= ÀlinestateðokayG+otg-port Á0=ghjÀotg-bvalidotg-idlinestateðokayG0usb2phy@e460rockchip,rk3399-usb2phyÃä`è|äphyclk‚oclk_usbphy1_480m ðdisabledG-host-port Á= ÀlinestateðokayG.otg-port Á0=lmoÀotg-bvalidotg-idlinestateðokayG2phy@f780rockchip,rk3399-emmc-phyÃ÷€$è”äemmcclk Ì2 ÁðokayG)pcie-phyrockchip,rk3399-pcie-phyèŠärefclk Á‡%phyðokayGphy@ff7c0000rockchip,rk3399-typec-phyÃÿ|è~}ätcpdcoretcpdphy-refé~ùúð€ª•”L%uphyuphy-pipeuphy-tcphy¸ ðokayû/dp-port ÁG4usb3-port ÁG1phy@ff800000rockchip,rk3399-typec-phyÃÿ€è€ätcpdcoretcpdphy-refé€ùúð€ª �œM%uphyuphy-pipeuphy-tcphy¸  ðdisableddp-port Áusb3-port ÁG3watchdog@ff848000 rockchip,rk3399-wdtsnps,dw-wdtÃÿ„€è|=xrktimer@ff850000rockchip,rk3399-timerÃÿ…=QèhZ äpclktimerspdif@ff870000rockchip,rk3399-spdifÃÿ‡=B�`”tx ämclkhclkèUת¨ðokayGÔi2s@ff880000(rockchip,rk3399-i2srockchip,rk3066-i2sÃÿˆ¸ ='�``”txrxäi2s_clki2s_hclkèVÔ:defaultH•ª¨ðokayGÓi2s@ff890000(rockchip,rk3399-i2srockchip,rk3066-i2sÃÿ‰=(�``”txrxäi2s_clki2s_hclkèWÕ:defaultH–ª¨ ðdisabledi2s@ff8a0000(rockchip,rk3399-i2srockchip,rk3066-i2sÃÿŠ=)�``”txrxäi2s_clki2s_hclkèXÖª¨ ðdisabledG©vop@ff8f0000rockchip,rk3399-vop-litÃÿ�>ü=wéÛÛùׄõáèÛµÛäaclk_vopdclk_vophclk_vop G—ª %axiahbdclkðokayport+Gendpoint@0ù˜G®endpoint@1ù™Gºendpoint@2ùšG¬endpoint@3ù›G¶endpoint@4ùœG6iommu@ff8f3f00rockchip,iommuÃÿ�?=wèÛÛ äaclkifaceª NðokayG—vop@ff900000rockchip,rk3399-vop-bigÃÿ�>ü=véÙÙùׄõáèÙ´Ùäaclk_vopdclk_vophclk_vop G�ª %axiahbdclkðokayport+Gendpoint@0ùžG¹endpoint@1ùŸG­endpoint@2ù G«endpoint@3ù¡Gµendpoint@4ù¢G5iommu@ff903f00rockchip,iommuÃÿ�?=vèÙÙ äaclkifaceª NðokayG�isp0@ff910000rockchip,rk3399-cif-ispÃÿ‘@=+ènéãäispaclkhclk G£¤ dphyªðokayports+port@0Ã+endpoint@0ù¥mGFendpoint@1ù¦mGHiommu@ff914000rockchip,iommu Ãÿ‘@ÿ‘P=+èéã äaclkiface Nª àðokayG£isp1@ff920000rockchip,rk3399-cif-ispÃÿ’@=,èoêääispaclkhclk G§¨ dphyª ðdisabledports+port@0Ã+iommu@ff924000rockchip,iommu Ãÿ’@ÿ’P=,èêä äaclkiface Nª àG§hdmi-soundsimple-audio-card ûi2s  .hdmi-sound ðdisabledsimple-audio-card,cpu E©simple-audio-card,codec Eªhdmi@ff940000rockchip,rk3399-dw-hdmiÃÿ”=(ètqpoäiahbisfrcecgrfrefª‚¸ ¨ ðdisabledGªportsport+endpoint@0ù«G endpoint@1ù¬Gšmipi@ff960000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsiÃÿ–€=- è¢p£oärefpclkphy_cfggrfªû%apb¸ +ðokay Oports+port@0Ã+endpoint@0ù­GŸendpoint@1ù®G˜port@1Ãendpoint¹¯G³panel@0à \° f±:defaultH²kingdisplay,kd097d04 sŒports+port@0Ãendpoint¹³G¯port@1Ãendpoint@1¹´G·mipi@ff968000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsiÃÿ–€€=. è¢q¤oärefpclkphy_cfggrfªü%apb¸ + ÁðokayG¨ports+port@0Ã+endpoint@0ùµG¡endpoint@1ù¶G›port@1Ãendpoint¹·G´edp@ff970000rockchip,rk3399-edpÃÿ—€= èjlo ädppclkgrf:defaultH¸ª%dp¸  ðdisabledports+port@0Ã+endpoint@0ù¹Gžendpoint@1ùºG™gpu@ff9a0000#rockchip,rk3399-maliarm,mali-t860Ãÿš0= ÀjobmmugpuèÐïª#ðokay(» €¼Gjpinctrlrockchip,rk3399-pinctrl¸ È+:default H½¾¿gpio@ff720000rockchip,gpio-bankÃÿrè‚= Œ œ•™â ¨CLK_32K_APEC_IN_RW_ODSPK_PA_ENWLAN_PERST_1V8_LWLAN_PD_1V8_LWLAN_RF_KILL_1V8_LBIGCPU_DVS_PWMSD_CD_L_JTAG_ENBT_EN_BT_RF_KILL_1V8_LPMUIO2_33_18_L_PP3300_S0_ENTOUCH_RESET_LAP_EC_WARM_RESET_REQPEN_RESET_LAP_FLASH_WP_LGgpio@ff730000rockchip,gpio-bankÃÿsè‚= Œ œ•™‰ ¨PEN_INT_ODLPEN_EJECT_ODLBT_HOST_WAKE_1V8_LWLAN_HOST_WAKE_1V8_LTOUCH_INT_ODLAP_EC_S3_S0_LAP_EC_OVERTEMPAP_SPI_FLASH_MISOAP_SPI_FLASH_MOSI_RAP_SPI_FLASH_CLK_RAP_SPI_FLASH_CS_L_RSD_CARD_DET_ODLAP_EXPANSION_IO1AP_EXPANSION_IO2AP_I2C_DISP_SDAAP_I2C_DISP_SCLH1_INT_ODLEC_AP_INT_ODLLITCPU_DVS_PWMAP_I2C_AUDIO_SDAAP_I2C_AUDIO_SCLAP_EXPANSION_IO3HEADSET_INT_ODLAP_EXPANSION_IO4G&gpio@ff780000rockchip,gpio-bankÃÿxèP= Œ œ•™  ¨AP_I2C_PEN_SDAAP_I2C_PEN_SCLSD_IO_PWR_ENUCAM_RST_LPP1250_CAM_ENWCAM_RST_LAP_EXPANSION_IO5AP_I2C_CAM_SDAAP_I2C_CAM_SCLAP_H1_SPI_MISOAP_H1_SPI_MOSIAP_H1_SPI_CLKAP_H1_SPI_CS_LUART_EXPANSION_TX_AP_RXUART_AP_TX_EXPANSION_RXUART_EXPANSION_RTS_AP_CTSUART_AP_RTS_EXPANSION_CTSAP_SPI_EC_MISOAP_SPI_EC_MOSIAP_SPI_EC_CLKAP_SPI_EC_CS_LPP2800_CAM_ENCLK_24M_CAMWLAN_PCIE_CLKREQ_1V8_LSD_PWR_3000_1800_LGEgpio@ff788000rockchip,gpio-bankÃÿx€èQ= Œ œ•™‚ ¨I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDI_0STRAP_LCDBIAS_LSTRAP_FEATURE_1STRAP_FEATURE_2I2S0_SDO_0gpio@ff790000rockchip,gpio-bankÃÿyèR= Œ œ•™Ü ¨I2S_MCLKAP_I2C_EXPANSION_SDAAP_I2C_EXPANSION_SCLDMIC_ENAP_I2C_TS_SDAAP_I2C_TS_SCLGPU_DVS_PWMUART_DBG_TX_AP_RXUART_AP_TX_DBG_RXBL_ENBL_PWMDISPLAY_RST_LPPVARP_LCD_ENPPVARN_LCD_ENSD_SLOT_PWR_ENG±pcfg-pull-up ¸GÄpcfg-pull-down ÅGÆpcfg-pull-none ÔGÀpcfg-pull-none-12ma Ô á GÂpcfg-pull-none-13ma Ô á GÁpcfg-pull-none-18ma Ô ápcfg-pull-none-20ma Ô ápcfg-pull-up-2ma ¸ ápcfg-pull-up-8ma ¸ ápcfg-pull-up-18ma ¸ ápcfg-pull-up-20ma ¸ ápcfg-pull-down-4ma Å ápcfg-pull-down-8ma Å ápcfg-pull-down-12ma Å á pcfg-pull-down-18ma Å ápcfg-pull-down-20ma Å ápcfg-output-high ðGÇpcfg-output-low üpcfg-input-enable pcfg-input-pull-up  ¸ ápcfg-input-pull-down  Å áclockclk-32k ÀG¾cifcif-clkin  Àcif-clkouta  Àedpedp-hpd ÀG¸gmacrgmii-pinsð ÁÀ À Á À ÀÀÀÀÁÁÀÀÁÁrmii-pins   À Á À À ÀÀÀÀÁÁi2c0i2c0-xfer ÀÀGˆi2c1i2c1-xfer ÀÀG7i2c2i2c2-xfer ÂÂG8i2c3i2c3-xfer ÀÀG;i2c4i2c4-xfer  À ÀG‰i2c5i2c5-xfer  À ÀG>i2c6i2c6-xfer  À ÀG?i2c7i2c7-xfer ÀÀG@i2c8i2c8-xfer ÀÀGŠi2s0i2s0-2ch-bus` ÀÀÀÀÀÀi2s0-8ch-bus` ÃÃÃÃÃÃG•i2s1i2s1-2ch-busP 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compatibleinterrupt-parent#address-cells#size-cellschassis-typemodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4mmc0mmc1cpudevice_typeregenable-methodcapacity-dmips-mhzclocks#cooling-cellsdynamic-power-coefficientcpu-idle-statesoperating-points-v2cpu-supplyphandleduration-usexit-latency-usentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usmin-residency-usportsrockchip,pmudevfreq-eventsclock-namesstatusrockchip,pd-idle-nsrockchip,sr-idle-nsrockchip,sr-mc-gate-idle-nsrockchip,srpd-lite-idle-nsrockchip,standby-idle-nsrockchip,ddr3_odt_dis_freqrockchip,lpddr3_odt_dis_freqrockchip,lpddr4_odt_dis_freqrockchip,sr-mc-gate-idle-dis-freq-hzrockchip,srpd-lite-idle-dis-freq-hzrockchip,standby-idle-dis-freq-hzcenter-supplyinterruptsarm,no-tick-in-suspendclock-frequencyclock-output-names#clock-cellsreg-names#interrupt-cellsaspm-no-l0sbus-rangeinterrupt-namesinterrupt-map-maskinterrupt-mapmax-link-speedmsi-mapphysphy-namesrangesresetsreset-namesep-gpiospinctrl-namespinctrl-0vpcie3v3-supplyvpcie1v8-supplyvpcie0v9-supplypcie-reset-suspendinterrupt-controllerpower-domainsrockchip,grfsnps,txpblmax-frequencyfifo-depthassigned-clocksassigned-clock-ratesbus-widthcap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplyarasan,soc-ctl-syscondisable-cqe-dcmdmmc-hs400-1_8vmmc-hs400-enhanced-strobenon-removableextcondr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirk#sound-dai-cellsremote-endpointmsi-controller#msi-cellsaffinity#io-channel-cellsi2c-scl-falling-time-nsi2c-scl-rising-time-nshid-descr-addrreset-gpiosavdd-supplydvdd-supplydovdd-supplydata-lanesreg-shiftreg-io-widthdmasdma-namespinctrl-1spi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countgoogle,usb-port-idkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymappolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#power-domain-cellspm_qospmu1830-supplydlg,micbias-lvldlg,mic-amp-in-selVDD-supplyVDDMIC-supplyVDDIO-supplydlg,adc-1bit-rptdlg,btn-avgdlg,btn-cfgdlg,mic-det-thrdlg,jack-ins-debdlg,jack-det-ratedlg,jack-rem-debdlg,a-d-btn-thrdlg,d-b-btn-thrdlg,b-c-btn-thrdlg,c-mic-btn-thr#pwm-cellsiommus#iommu-cells#dma-cellsarm,pl330-periph-burst#reset-cellsaudio-supplybt656-supplygpio1830-supplysdmmc-supply#phy-cellsdrive-impedance-ohmrockchip,disable-mmu-resetsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namesound-daiclock-masterbacklightenable-gpiospower-supplymali-supplygpio-controller#gpio-cellsgpio-line-namesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplypwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitctrl-supplyctrl-voltage-rangeregulator-settling-time-up-usenable-active-highgpioenable-gpiosdmode-gpiossdmode-delayrockchip,cpurockchip,codecstartup-delay-usregulator-enable-ramp-delaypwm-delay-usdmicen-gpioswakeup-delay-mslabellinux,codelinux,input-typewakeup-source