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Émpp4mpp5ÖgeSref-clk-pins-0Émpp45Örefref-clk-pins-1Émpp46Örefspi-pins-0Émpp22mpp23mpp24mpp25Öspi0Sspi-pins-1Émpp56mpp57mpp58mpp59Öspi1nand-pinsNÉmpp22mpp34mpp23mpp33mpp38mpp28mpp40mpp42mpp35mpp36mpp25mpp30mpp32Ödevnand-rbÉmpp41Önanduart-pins-0 Émpp0mpp1Öua0Suart-pins-1 Émpp19mpp20Öua1S sdhci-pins<Émpp48mpp49mpp50mpp52mpp53mpp54mpp55mpp57mpp58mpp59Ösd0Ssata-pins-0Émpp20Ösata0sata-pins-1Émpp19Ösata1sata-pins-2Émpp47Ösata2sata-pins-3Émpp44Ösata3pcawan-pinsÉmpp46ÖgpioSswint-pinsÉmpp45ÖgpioSspi0cs0-pinsÉmpp25Öspi0Sspi0cs1-pinsÉmpp26Öspi0gpio@18100+!marvell,armada-370-gpiomarvell,orion-gpio¢�@�À çgpiopwmñ –¦ø>-0"5678¦gpio@18140+!marvell,armada-370-gpiomarvell,orion-gpio¢�@@�È çgpiopwmñ–¦ø>-0":;<=¦Ssystem-controller@18200M!marvell,armada-380-system-controllermarvell,armada-370-xp-system-controller¢‚clock-gating-control@18220 !marvell,armada-380-gating-clock¢‚ ¦S phy@18300!marvell,armada-380-comphy çcomphyconf¢ƒ„`phy@0¢phy@1¢phy@2¢phy@3¢phy@4¢phy@5¢Smvebu-sar@18600!marvell,armada-380-core-clock¢†Smbus-controller@20000!marvell,mbus-controller¢€ PSinterrupt-controller@20a00 !marvell,mpic¢ ÐpX-> "Stimer@203001!marvell,armada-380-timermarvell,armada-xp-timer¢0@0PH    ¦  *nbclkfixedwatchdog@20300!marvell,armada-380-wdt¢4‚` ¦  *nbclkfixed H@ cpurst@20800!marvell,armada-370-cpu-reset¢mpcore-soc-ctrl@20d20#!marvell,armada-380-mpcore-soc-ctrl¢ lcoherency-fabric@21010$!marvell,armada-380-coherency-fabric¢pmsu@22000!marvell,armada-380-pmsu¢ ethernet@70000!marvell,armada-370-neta¢@H¦ 6&H­okay[defaulti DrgmiiM \ifixed-linkwè}ethernet@30000!marvell,armada-370-neta¢@H ¦ ­okay[defaultiDrgmiiM \iSfixed-linkwè}ethernet@34000!marvell,armada-370-neta¢@@H ¦ ­okayDsgmii‰”™M \iusb@58000!marvell,orion-ehci¢€ "¦ ­okayxor@60800)!marvell,armada-380-xormarvell,orion-xor¢ ¦ ­okayxor00 "�«xor01 "�«¶xor@60900)!marvell,armada-380-xormarvell,orion-xor¢  ¦ ­okayxor10 "A�«xor11 "B�«¶mdio@72004!marvell,orion-mdio¢ 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#address-cells#size-cellsmodelcompatiblegpio0gpio1serial0serial1interrupts-extendedcontrollerinterrupt-parentpcie-mem-aperturepcie-io-aperturerangesregclocksstatuscache-unifiedcache-levelarm,double-linefill-incrarm,double-linefill-wraparm,double-linefillprefetch-datainterrupts#interrupt-cellsinterrupt-controllerphandlepinctrl-namespinctrl-0colorfunctionfunction-enumeratorgpio-controller#gpio-cellsreg-shiftreg-io-widthmarvell,pinsmarvell,functionreg-namesngpios#pwm-cells#clock-cells#phy-cellsmsi-controllerclock-namestx-csum-limitphy-modebuffer-managerbm,pool-longbm,pool-shortspeedfull-duplexphy-handlephyssfpdmacap,memcpydmacap,xordmacap,memsetmarvell,reg-initdsa,memberlabelethernetmarvell,crypto-sramsmarvell,crypto-sram-sizeinternal-memclock-output-namesmrvl,clk-delay-cyclesbus-widthno-1-8-vnon-removableno-memory-wccell-indexspi-max-frequencydevice_typemsi-parentbus-rangeassigned-addressesinterrupt-namesinterrupt-map-maskinterrupt-mapmarvell,pcie-portmarvell,pcie-laneslot-power-limit-milliwattclock-frequencyenable-methodstdout-pathi2c-bustx-fault-gpiostx-disable-gpiosrate-select0-gpioslos-gpiosmod-def0-gpiosmaximum-power-milliwatt