Ð þí>\8: (P9Ô$rockchip,rk3036-evbrockchip,rk3036&!7Rockchip RK3036 Evaluation boardaliases=/i2c@20072000B/i2c@20056000G/i2c@2005a000L/mmc@1021c000R/mmc@10214000X/mmc@10218000^/serial@20060000f/serial@20064000n/serial@20068000v/spi@20074000cpuszrockchip,rk3036-smpcpu@f00ˆcpuarm,cortex-a7”˜Ÿ s€B@°œ@¾Åcpu@f01ˆcpuarm,cortex-a7”˜Åarm-pmuarm,cortex-a7-pmuÍLMØdisplay-subsystemrockchip,display-subsystemëtimerarm,armv7-timerñ0Í   n6oscillator fixed-clockn6%xin24m8Åsram@10080000 mmio-sram”  E smp-sram@0rockchip,rk3066-smp-sram”gpu@10090000"rockchip,rk3036-maliarm,mali-400” 0ÍLgpgpmmupp0ppmmu0\@lõá¾@@ �buscore�˜x ›disabledvideo-codec@10108000rockchip,rk3036-vpu”€ ÍLvdpu¾ÐÜ �aclkhclk¢�iommu@10108800rockchip,iommu”ˆ Í7¾ÐÜ �aclkiface�©Åvop@10118000rockchip,rk3036-vop”€œ Í+¾ÅdÑ�aclk_vopdclk_vophclk_vop˜uvw ¶axiahbdclk¢� ›disabledportÅendpoint@0” Å iommu@10118300rockchip,iommu”ƒ Í+¾ÅÑ �aclkiface�© ›disabledÅqos@1012d000rockchip,rk3036-qossyscon”Ð Åqos@1012e000rockchip,rk3036-qossyscon”à Åqos@1012f000rockchip,rk3036-qossyscon”ð Åinterrupt-controller@10139000 arm,gic-400Òç ”�  À à  Í Åusb@101800002rockchip,rk3036-usbrockchip,rk3066-usbsnps,dwc2” Í ¾Á�otgøotg!€€@@  ›disabledusb@101c00002rockchip,rk3036-usbrockchip,rk3066-usbsnps,dwc2” Í ¾Â�otgøhost ›disabledethernet@10200000#rockchip,rk3036-emacsnps,arc-emac” @ Í0 ¾Ì˜—�hclkmacrefmacclk\™=Td^rmii›okaygdefaultu   ƒ“ ethernet-phy@0”Å mmc@102140000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc”!@@<4`¦<4`¾ÈD�biuciu´ ͘Q¶reset ›disabledmmc@102180000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc”!€@¦<4` ¾ÉEsw�biuciuciu-driveciu-sample´ ͘R¶reset ›disabledmmc@1021c0000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc”!À@ Í¿É<4`¦<4` ¾ËGuy�biuciuciu-driveciu-sampleÛžù  rx-tx´ gdefault u˜S¶reset ›disabledi2s@10220000(rockchip,rk3036-i2srockchip,rk3066-i2s”"@ Í3�i2s_clki2s_hclk¾RÎ txrxgdefaultu. ›disablednand-controller@10500000(rockchip,rk3036-nfcrockchip,rk2928-nfc”P@ ;ÅL�ahbnfc\LlðÑ€ugdefault ›disabledclock-controller@20000000rockchip,rk3036-cru” ¾�xin24m0 8?\l#g¸€Åsyscon@20008000&rockchip,rk3036-grfsysconsimple-mfd” €Å power-controller!rockchip,rk3036-power-controllerLÅpower-domain@3”¾ÅÑd`Lpower-domain@4”¾ÐÜ`Lpower-domain@5”¾@`Lreboot-modesyscon-reboot-modegØnRBÃzRBÈRBà ˜RBÃacodec-ana@20030000 rk3036-codec” @0  �acodec_pclk¾q ›disabledhdmi@20034000rockchip,rk3036-inno-hdmi” @@ Í-¾h�pclk0 gdefaultu ›disabledportendpoint@0” Å timer@20044000,rockchip,rk3036-timerrockchip,rk3288-timer” @  Í ¾a �pclktimerpwm@20050000(rockchip,rk3036-pwmrockchip,rk2928-pwm” ¤¾^gdefaultu! ›disabledpwm@20050010(rockchip,rk3036-pwmrockchip,rk2928-pwm” ¤¾^gdefaultu" ›disabledpwm@20050020(rockchip,rk3036-pwmrockchip,rk2928-pwm”  ¤¾^gdefaultu# ›disabledpwm@20050030(rockchip,rk3036-pwmrockchip,rk2928-pwm” 0¤¾^gdefaultu$ ›disabledi2c@20056000(rockchip,rk3036-i2crockchip,rk3288-i2c” ` Í�i2c¾Mgdefaultu%›okayhym8563@51haoyu,hym8563”Q8€%xin32ki2c@2005a000(rockchip,rk3036-i2crockchip,rk3288-i2c”   Í�i2c¾Ngdefaultu& ›disabledserial@20060000&rockchip,rk3036-uartsnps,dw-apb-uart”  ͯ¹n6¾MU�baudclkapb_pclkgdefault u'() ›disabledserial@20064000&rockchip,rk3036-uartsnps,dw-apb-uart” @ ͯ¹n6¾NV�baudclkapb_pclkgdefaultu* ›disabledserial@20068000&rockchip,rk3036-uartsnps,dw-apb-uart” € ͯ¹n6¾OW�baudclkapb_pclkgdefaultu+›okayi2c@20072000(rockchip,rk3036-i2crockchip,rk3288-i2c”   Í�i2c¾Lgdefaultu, ›disabledspi@20074000rockchip,rockchip-spi” @ ;RA�apb-pclkspi_pclk  txrxgdefaultu-./0 ›disableddma-controller@20078000arm,pl330arm,primecell” €@ÍÆÑì¾Â �apb_pclkÅpinctrlrockchip,rk3036-pinctrl0 Egpio@2007c000rockchip,gpio-bank” À Í$¾@Òçgpio@20080000rockchip,gpio-bank”  Í%¾AÒçgpio@20084000rockchip,gpio-bank” @ Í&¾BÒçÅpcfg-pull-defaultÅ2pcfg-pull-none5Å1pwm0pwm0-pinB1Å!pwm1pwm1-pinB1Å"pwm2pwm2-pinB1Å#pwm3pwm3-pinB1Å$sdmmcsdmmc-clkB1sdmmc-cmdB2sdmmc-cdB2sdmmc-bus1B2sdmmc-bus4@B2222sdiosdio-bus1B 2sdio-bus4@B 2 2 22sdio-cmdB2sdio-clkB 1emmcemmc-clkB1Åemmc-cmdB2Åemmc-bus8€B22222222Ånfcflash-aleB2Åflash-bus8€B22222222Åflash-cleB2Åflash-csn0B2Åflash-rdnB2Åflash-rdyB2Åflash-wrnB2Åemacemac-xfer€B 2 2222222Å emac-mdio B 22Å i2c0i2c0-xfer B11Å,i2c1i2c1-xfer B11Å%i2c2i2c2-xfer B11Å&i2si2s-bus`B222222Åhdmihdmi-ctl@B1 1 1 1Åuart0uart0-xfer B21Å'uart0-ctsB2Å(uart0-rtsB1Å)uart1uart1-xfer B21Å*uart2uart2-xfer B21Å+spi-pinsspi-txdB2Å-spi-rxdB2Å.spi-clkB2Å/spi-cs0B2Å0spi-cs1B2memory@60000000ˆmemory”`@ #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2mshc0mshc1mshc2serial0serial1serial2spienable-methoddevice_typeregresetsoperating-pointsclock-latencyclocksphandleinterruptsinterrupt-affinityportsarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsrangesinterrupt-namesassigned-clocksassigned-clock-ratesclock-namespower-domainsstatusiommus#iommu-cellsreset-namesremote-endpointinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,grfassigned-clock-parentsmax-speedphy-modepinctrl-namespinctrl-0phyphy-reset-gpiosphy-reset-durationmax-frequencyfifo-depthbus-widthcap-mmc-highspeedrockchip,default-sample-phasedisable-wpdmasdma-namesmmc-ddr-1_8vnon-removable#sound-dai-cells#reset-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#pwm-cellsreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pins