Ð þíb¯8\ø(·\À ,Freescale i.MX8DXL EVK2fsl,imx8dxl-evkfsl,imx8dxlaliases =/bus@5b000000/ethernet@5b040000 G/bus@5b000000/ethernet@5b050000Q/bus@5d000000/gpio@5d080000W/bus@5d000000/gpio@5d090000]/bus@5d000000/gpio@5d0a0000c/bus@5d000000/gpio@5d0b0000i/bus@5d000000/gpio@5d0c0000o/bus@5d000000/gpio@5d0d0000u/bus@5d000000/gpio@5d0e0000{/bus@5d000000/gpio@5d0f0000�/bus@5d000000/mailbox@5d1c0000…/bus@5a000000/i2c@5a820000Š/bus@5b000000/mmc@5b010000�/bus@5b000000/mmc@5b020000”/bus@5a000000/serial@5a060000cpus cpu@0œcpu2arm,cortex-a35¨¬psciº ËûÒáõ cpu@1œcpu2arm,cortex-a35¨¬psciº ËûÒáõ l2-cache02cacheõopp-table2operating-points-v2ýõopp-9000000005¤éB@Iðopp-1200000000G†ŒÈàIð.interrupt-controller@51a00000 2arm,gic-v3 ¨Q Q° :K ` õreserved-memory kdsp@92400000¨’@rõlinux,cma2shared-dma-pooly‚‡˜”pmu2arm,armv8-pmuv3 `psci 2arm,psci-1.0³smcsystem-controller 2fsl,imx-scu ¦tx0rx0gip3$±power-controller 2fsl,scu-pd¸8Ì £ëìíäåæçîïð¦©õclock-controller2fsl,imx8dxl-clkfsl,scu-clk×Ëäxtal_32KHzxtal_24Mhzõpinctrl2fsl,imx8dxl-iomuxcðdefaultþhoggrp0< I @LkLõusbotg1grp !usbotg2grp !eqosgrp¨- , 3 9 6 5 4 : / 7 8 0 2 1 õ.fec1grpÀ# * - , $`&`'`(`)`%``` `!`"``õ(lpspi3grp0=@>@?@A@i2c2grps!t!õcm40lpuartgrpS R i2c3grpv!u!lpuart0grp\ ] õusdhc1grp„ A ! ! ! !!!!!!Aõ usdhc2gpiogrp$@ !!!õ#usdhc2grpT$A%!&!'!(!)!!õ"ocotp2fsl,imx8qxp-scu-ocotp mac@2c4¨Äõ*mac@2c6¨Æõ0rtc2fsl,imx8qxp-sc-rtckeys"2fsl,imx8qxp-sc-keyfsl,imx-sc-keyt watchdog2fsl,imx-sc-wdt.<thermal-sensor2fsl,imx-sc-thermal:õ timer2arm,armv8-timer0`   thermal-zonescpu-thermal0PúfÐt ctripstrip0„¡ø�Уpassiveõ trip1„ð�Ð £criticalcooling-mapsmap0›   ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿpmic-thermal0PúfÐt ñtripstrip0„­°�Уpassiveõ trip1„èH�Ð £criticalcooling-mapsmap0›   ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿclock-xtal32k 2fixed-clockׯ€ ¿xtal_32KHzõclock-xtal24m 2fixed-clockׯn6 ¿xtal_24MHzõbus@59000000 2simple-bus kYYclock-audio-ipg 2fixed-clockׯ ‰h¿audio_ipg_clkõclock-controller@595800002fsl,imx8qxp-lpcg¨YX× Ë Ò4¿dsp_lpcg_adb_clkdsp_lpcg_ipg_clkdsp_lpcg_core_clkàõclock-controller@595900002fsl,imx8qxp-lpcg¨YY×ËÒ¿dsp_ram_lpcg_ipg_clkàõdsp@596e80002fsl,imx8qxp-dsp¨Yn€€Ëäipgocramcore àâë¦txdb0txdb1rxdb0rxdb10±î üdisabledbus@5a000000 2simple-bus kZZclock-dma-ipg 2fixed-clockׯ ‰h ¿dma_ipg_clkõserial@5a060000¨Z `äË äipgbaud 9Ä´à9üokay&2fsl,imx8qxp-lpuartfsl,imx7ulp-lpuartðdefaultþserial@5a070000¨Z `åË äipgbaud :Ä´à: üdisabled&2fsl,imx8qxp-lpuartfsl,imx7ulp-lpuartserial@5a080000¨Z `æË äipgbaud ;Ä´à; üdisabled&2fsl,imx8qxp-lpuartfsl,imx7ulp-lpuartserial@5a090000¨Z  `çË äipgbaud <Ä´à< üdisabled&2fsl,imx8qxp-lpuartfsl,imx7ulp-lpuartclock-controller@5a4600002fsl,imx8qxp-lpcg¨ZF×Ë9Ò'¿uart0_lpcg_baud_clkuart0_lpcg_ipg_clkà9õclock-controller@5a4700002fsl,imx8qxp-lpcg¨ZG×Ë:Ò'¿uart1_lpcg_baud_clkuart1_lpcg_ipg_clkà:õclock-controller@5a4800002fsl,imx8qxp-lpcg¨ZH×Ë;Ò'¿uart2_lpcg_baud_clkuart2_lpcg_ipg_clkà;õclock-controller@5a4900002fsl,imx8qxp-lpcg¨ZI×Ë<Ò'¿uart3_lpcg_baud_clkuart3_lpcg_ipg_clkà<õi2c@5a800000¨Z€@ `ÞËäperipg `n6à` üdisabled62fsl,imx8dxl-lpi2cfsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2ci2c@5a810000¨Z�@ `ßËäperipg an6àa üdisabled62fsl,imx8dxl-lpi2cfsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2ci2c@5a820000¨Z‚@ `àËäperipg bn6àbüokay$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2c ¯† ðdefaultþgpio@20 2ti,tca6416¨ (8õ+gpio@21 2ti,tca6416¨!(8õ:i2c-mux@70 2nxp,pca9548 ¨pi2c@0 ¨gpio@682maxim,max7322¨h(8 üdisabledõ;i2c@4 ¨i2c@5 ¨i2c@6 ¨i2c@5a830000¨Zƒ@ `áËäperipg cn6àc üdisabled$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2cclock-controller@5ac000002fsl,imx8qxp-lpcg¨ZÀ×Ë`Ò ¿i2c0_lpcg_clki2c0_lpcg_ipg_clkà`õclock-controller@5ac100002fsl,imx8qxp-lpcg¨ZÁ×ËaÒ ¿i2c1_lpcg_clki2c1_lpcg_ipg_clkàaõclock-controller@5ac200002fsl,imx8qxp-lpcg¨ZÂ×ËbÒ ¿i2c2_lpcg_clki2c2_lpcg_ipg_clkàbõclock-controller@5ac300002fsl,imx8qxp-lpcg¨ZÃ×ËcÒ ¿i2c3_lpcg_clki2c3_lpcg_ipg_clkàcõbus@5b000000 2simple-bus k[[clock-conn-axi 2fixed-clockׯÞCU ¿conn_axi_clkõ3clock-conn-ahb 2fixed-clockׯ ï!ª ¿conn_ahb_clkclock-conn-ipg 2fixed-clockׯ÷�Õ ¿conn_ipg_clkõ2mmc@5b010000 `Ѝ[Ë äipgahbperàøüokay$2fsl,imx8dxl-usdhcfsl,imx8qxp-usdhcðdefaultþ DNT\mmc@5b020000 `‹¨[Ë!!! äipgahbperàùjüokay$2fsl,imx8dxl-usdhcfsl,imx8qxp-usdhcðdefaultþ"#D�$ ›% ¤%mmc@5b030000 `Œ¨[Ë&&& äipgahbperàú üdisabled$2fsl,imx8dxl-usdhcfsl,imx8qxp-usdhcethernet@5b040000¨[0` žŸ¡ Ë''' 'äipgahbenet_clk_refptp ûsY@­¿àû üdisabled2fsl,imx8qm-fecðdefaultþ( Ñrgmii-txidÚ)åöÐ * mac-addressmdio ethernet-phy@12ethernet-phy-ieee802.3-c22¨ (+4'DY,õ)vddio-regulatorfw@~w@õ,ethernet@5b050000¨[`£¢(Ë-----ästmmacethpclkptp_reftxmem üsY@àüüokay(2nxp,imx8dxl-dwmac-eqossnps,dwmac-5.10a–eth_wake_irqmacirqðdefaultþ. Ñrgmii-idÚ/ 0 mac-addressmdio2snps,dwmac-mdio ethernet-phy@02ethernet-phy-ieee802.3-c22¨¦D· (+4Ô @Y1õ/vddio-regulatorfw@~w@õ1clock-controller@5b2000002fsl,imx8qxp-lpcg¨[ ×Ëø23 Ò9¿sdhc0_lpcg_per_clksdhc0_lpcg_ipg_clksdhc0_lpcg_ahb_clkàøõclock-controller@5b2100002fsl,imx8qxp-lpcg¨[!×Ëù23 Ò9¿sdhc1_lpcg_per_clksdhc1_lpcg_ipg_clksdhc1_lpcg_ahb_clkàùõ!clock-controller@5b2200002fsl,imx8qxp-lpcg¨["×Ëú23 Ò9¿sdhc2_lpcg_per_clksdhc2_lpcg_ipg_clksdhc2_lpcg_ahb_clkàúõ&clock-controller@5b2300002fsl,imx8qxp-lpcg¨[#× Ë443û22Ò …¿enet0_lpcg_timer_clkenet0_lpcg_txc_sampling_clkenet0_lpcg_ahb_clkenet0_lpcg_rgmii_txc_clkenet0_lpcg_ipg_clkenet0_lpcg_ipg_s_clkàûõ'clock-controller@5b2400002fsl,imx8qxp-lpcg¨[$×Ë433ü2Ò6¿eqos_ptpeqos_mem_clkeqos_aclkeqos_clkeqos_csr_clkàüõ-clock-conn-enet0-root 2fixed-clockׯ沀¿conn_enet0_root_clkõ4usb@5b0e0000 2fsl,imx8dxl-usbfsl,imx7ulp-usb¨[ `¦æ5ñ6Ë7ý"6à üdisabledclock-dummy 2fixed-clockׯ ¿clk_dummyõ7usbmisc@5b0e0200G2fsl,imx7ulp-usbmisc¨[õ6usbphy@0x5b110000&2fsl,imx8dxl-usbphyfsl,imx7ulp-usbphy¨[Ë8à üdisabledõ5clock-controller@5b2800002fsl,imx8qxp-lpcg¨[(×ÒË2¿usboh3_2_phy_ipg_clkàõ8bus@5c000000 2simple-bus k\\ddr-pmu@5c0200002fsl,imx8-ddr-pmu¨\ `Gbus@5d000000 2simple-bus k]]clock-lsio-mem 2fixed-clockׯ ë ¿lsio_mem_clkclock-lsio-bus 2fixed-clockׯõá ¿lsio_bus_clkõ9gpio@5d080000¨] `N(8K:àÇ 2fsl,imx8dxl-gpiofsl,imx35-gpiogpio@5d090000¨]  `O(8K:àÈ 2fsl,imx8dxl-gpiofsl,imx35-gpiogpio@5d0a0000¨]  `P(8K:àÉ 2fsl,imx8dxl-gpiofsl,imx35-gpiogpio@5d0b0000¨]  `Q(8K:àÊ 2fsl,imx8dxl-gpiofsl,imx35-gpiogpio@5d0c0000¨]  `R(8K:àË 2fsl,imx8dxl-gpiofsl,imx35-gpioüokayõ<gpio@5d0d0000¨]  `S(8K:àÌ 2fsl,imx8dxl-gpiofsl,imx35-gpioüokayõ%gpio@5d0e0000¨] `T(8K:àÍ 2fsl,imx8dxl-gpiofsl,imx35-gpiogpio@5d0f0000¨] `U(8K:àÎ 2fsl,imx8dxl-gpiofsl,imx35-gpiomailbox@5d1b0000¨] `VT üdisabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1c0000¨] `WT-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-muõmailbox@5d1d0000¨] `XT üdisabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1e0000¨] `YT üdisabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1f0000¨] `ZT üdisabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d200000¨]  `[TàÚ üdisabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d210000¨]! `¹TàÛ üdisabledmailbox@5d280000¨]( `ÀTàâõclock-controller@5d4000002fsl,imx8qxp-lpcg¨]@×4Ë¿¿¿9¿Òh¿pwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clkà¿clock-controller@5d4100002fsl,imx8qxp-lpcg¨]A×4ËÀÀÀ9ÀÒh¿pwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clkàÀclock-controller@5d4200002fsl,imx8qxp-lpcg¨]B×4ËÁÁÁ9ÁÒh¿pwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clkàÁclock-controller@5d4300002fsl,imx8qxp-lpcg¨]C×4ËÂÂÂ9ÂÒh¿pwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clkàÂclock-controller@5d4400002fsl,imx8qxp-lpcg¨]D×4ËÃÃÃ9ÃÒh¿pwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clkàÃclock-controller@5d4500002fsl,imx8qxp-lpcg¨]E×4ËÄÄÄ9ÄÒh¿pwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clkàÄclock-controller@5d4600002fsl,imx8qxp-lpcg¨]F×4ËÅÅÅ9ÅÒh¿pwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clkàÅclock-controller@5d4700002fsl,imx8qxp-lpcg¨]G×4ËÆÆÆ9ÆÒh¿pwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clkàÆchosen`/bus@5a000000/serial@5a060000memory@80000000œmemory¨€@regulator-02regulator-fixedf2Z ~2Z lmux3_en {:€regulator-12regulator-fixed lfec1_supplyf2Z ~2Z  {+ € üdisabledregulator-22regulator-fixedlfec1_io_supplyfw@~w@ {;”€ üdisabledregulator-32regulator-fixed lSD1_SPWRf-ÆÀ~-ÆÀ {<”§ ˜õ$ interrupt-parent#address-cells#size-cellsmodelcompatibleethernet0ethernet1gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7mu1i2c2mmc0mmc1serial0device_typeregenable-methodnext-level-cacheclocks#cooling-cellsoperating-points-v2phandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspend#interrupt-cellsinterrupt-controllerinterruptsrangesno-mapreusablesizealloc-rangeslinux,cma-defaultmbox-namesmboxes#power-domain-cellswakeup-irq#clock-cellsclock-namespinctrl-namespinctrl-0fsl,pinslinux,keycodeswakeup-sourcetimeout-sec#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceclock-frequencyclock-output-namesclock-indicespower-domainsmemory-regionstatusassigned-clocksassigned-clock-ratesgpio-controller#gpio-cellsbus-widthno-sdno-sdionon-removablefsl,tuning-start-tapfsl,tuning-stepvmmc-supplycd-gpioswp-gpiosfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetrx-internal-delay-psnvmem-cellsnvmem-cell-namesreset-gpiosreset-assert-usqca,disable-smarteeevddio-supplyregulator-min-microvoltregulator-max-microvoltinterrupt-nameseee-broken-1000tqca,disable-hibernation-modereset-deassert-usfsl,usbphyfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dword#stream-id-cells#index-cells#mbox-cellsstdout-pathregulator-namegpioregulator-always-onenable-active-highoff-on-delay-us