Ð þí‚h8{P({radxa,rockpisrockchip,rk3308 +7Radxa ROCK Pi Saliases=/i2c@ff040000B/i2c@ff050000G/i2c@ff060000L/i2c@ff070000Q/serial@ff0a0000Y/serial@ff0b0000a/serial@ff0c0000i/serial@ff0d0000q/serial@ff0e0000y/spi@ff120000~/spi@ff130000ƒ/spi@ff140000ˆ/ethernet@ff4e0000’/mmc@ff490000—/mmc@ff480000œ/mmc@ff4a0000cpus+cpu@0¡cpuarm,cortex-a35­±psci¿ÆÕZï$/cpu@1¡cpuarm,cortex-a35­±psciï/cpu@2¡cpuarm,cortex-a35­±psciï/ cpu@3¡cpuarm,cortex-a35­±psciï/ idle-states7pscicpu-sleeparm,idle-stateDUlx}ú�„/l2-cachecache/opp-table-0operating-points-v2ž/opp-408000000©Q– °~ð~ðr`¾œ@Ïopp-600000000©#ÃF °~ð~ðr`¾œ@opp-816000000©0£, °£è£èr`¾œ@opp-1008000000©<Ü °*ˆ*ˆr`¾œ@arm-pmuarm,cortex-a35-pmu0ÛSTUVæ external-mac-clock fixed-clockùúð€  mac_clkinpsci arm,psci-1.0¸smctimerarm,armv8-timer0Û   xin24m fixed-clockùn6 xin24m/]grf@ff000000&rockchip,rk3308-grfsysconsimple-mfd­ÿ€/Wreboot-modesyscon-reboot-mode)0RBÃ@RBÃLRBÃXRBÃfRBà syscon@ff008000.rockchip,rk3308-usb2phy-grfsysconsimple-mfd­ÿ€@+usb2phy@100rockchip,rk3308-usb2phy­t„ ¿H›phyclk  usb480m_phy§okay/ otg-port$ÛCDE®otg-bvalidotg-idlinestate¾§okayÉ />host-port ÛJ ®linestate¾§okayÉ /?syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd­ÿ°+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd­ÿÀ+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c­ÿ¿Ê ›i2cpclk Û Ôdefaultâ + §disabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c­ÿ¿Ë ›i2cpclk Û Ôdefaultâ+§okayi2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c­ÿ¿Ì ›i2cpclk Û Ôdefaultâ+ §disabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c­ÿ¿Í ›i2cpclk ÛÔdefaultâ+ §disabledwatchdog@ff080000 rockchip,rk3308-wdtsnps,dw-wdt­ÿ¿Ö Û §okayserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart­ÿ  Û¿Å›baudclkapb_pclkìöÔdefaultâ§okayserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart­ÿ  Û¿Æ›baudclkapb_pclkìöÔdefault â §disabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart­ÿ  Û¿Ç›baudclkapb_pclkìöÔdefaultâ §disabledserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart­ÿ  Û¿È›baudclkapb_pclkìöÔdefaultâ §disabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart­ÿ Û¿É›baudclkapb_pclkìöÔdefault â§okaybluetoothrealtek,rtl8723ds-bt   %  2 Ôdefault âspi@ff120000(rockchip,rk3308-spirockchip,rk3066-spi­ÿ Û+¿Ï›spiclkapb_pclkBGtxrxÔdefaultâ !" §disabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spi­ÿ Û+¿Ð›spiclkapb_pclkBGtxrxÔdefaultâ#$%& §disabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spi­ÿ Û+¿Ñ›spiclkapb_pclkB''GtxrxÔdefaultâ()*+ §disabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwm­ÿ¿yè ›pwmpclkÔdefaultâ,Q §disabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwm­ÿ¿yè ›pwmpclkÔdefaultâ-Q §disabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwm­ÿ ¿yè ›pwmpclkÔdefaultâ.Q §disabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwm­ÿ0¿yè ›pwmpclkÔdefaultâ/Q §disabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwm­ÿ¿xç ›pwmpclkÔdefaultâ0Q §disabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwm­ÿ¿xç ›pwmpclkÔdefaultâ1Q §disabledpwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwm­ÿ ¿xç ›pwmpclkÔdefaultâ2Q §disabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwm­ÿ0¿xç ›pwmpclkÔdefaultâ3Q §disabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm­ÿ¿Î ›pwmpclkÔdefaultâ4Q§okay/npwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm­ÿ¿Î ›pwmpclkÔdefaultâ5Q §disabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm­ÿ ¿Î ›pwmpclkÔdefaultâ6Q §disabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm­ÿ0¿Î ›pwmpclkÔdefaultâ7Q §disabledrktimer@ff1a0000rockchip,rk3288-timer­ÿ  Û¿Ô ›pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc­ÿ Û%¿%Ò›saradcapb_pclk\nF usaradc-apb§okay�8dma-controller@ff2c0000arm,pl330arm,primecell­ÿ,@Û�¿Š ›apb_pclk¤/dma-controller@ff2d0000arm,pl330arm,primecell­ÿ-@Û�¿‹ ›apb_pclk¤/'i2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s­ÿ5 Û4¿\¨›i2s_clki2s_hclkB'' Gtxrxn•”ureset-mreset-hÔdefaultâ9:;< §disabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s­ÿ6 Û5¿^©›i2s_clki2s_hclkB' Grxn—–ureset-mreset-h §disabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdif­ÿ: Û7¿b¢ ›mclkhclkB' GtxÔdefaultâ= §disabledusb@ff4000002rockchip,rk3308-usbrockchip,rk3066-usbsnps,dwc2­ÿ@ ÛB¿ž›otg ¯peripheral·ÉØ€€@ ç> ìusb2-phy§okayusb@ff440000 generic-ehci­ÿD ÛG¿Ÿ  ç?ìusb§okayusb@ff450000 generic-ohci­ÿE ÛH¿Ÿ  ç?ìusb§okaymmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshc­ÿH@ ÛLö ¿š012›biuciuciu-driveciu-sample ðÑ€Ôdefaultâ@ABC§okay+<GDmmc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshc­ÿI@ ÛMö ¿œ:;<›biuciuciu-driveciu-sample ðÑ€§okay+S[Ôdefault âEFGGDmmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshc­ÿJ@ ÛNö ¿›567›biuciuciu-driveciu-sample õáÔdefault âHIJ§okay++ivŒK—ž[¤GD±8wifi@1­ LÛ ®host-wakeÔdefaultâMnand-controller@ff4b0000(rockchip,rk3308-nfcrockchip,rv1108-nfc­ÿK@ ÛQ¿™-›ahbnfct-¾ðÑ€âNOPQRSTÔdefault §disabledethernet@ff4e0000rockchip,rk3308-gmac­ÿN Û@®macirq@¿@BBA@†ÃC[›stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedÓrmiiÔdefaultâUVn} ustmmacethÜW§okayéoutputöXÉDmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22­ÔdefaultâYN ÃP #L/Xspi@ff4c0000 rockchip,sfc­ÿL@ ÛR¿=�›clk_sfchclk_sfc âZ[\Ôdefault §disabledclock-controller@ff500000rockchip,rk3308-cru­ÿP¿]›xin24mÜW/t¾€/interrupt-controller@ff580000 arm,gic-400@­ÿXÿX ÿX@ ÿX`  Û <M/sram@fff80000 mmio-sram­ÿøbÿø+ddr-sram@0­€vad-sram@8000­€€pinctrlrockchip,rk3308-pinctrlÜW+bÔdefaultâ^gpio@ff220000rockchip,gpio-bank­ÿ" Û(¿×iyM</Lgpio@ff230000rockchip,gpio-bank­ÿ# Û)¿ØiyM<gpio@ff240000rockchip,gpio-bank­ÿ$ Û*¿ÙiyM<gpio@ff250000rockchip,gpio-bank­ÿ% Û+¿ÚiyM<gpio@ff260000rockchip,gpio-bank­ÿ& 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a/9i2s-2ch-0-lrcköa/:i2s-2ch-0-sdoöa/<i2s-2ch-0-sdiöa/;i2s_8ch_0i2s-8ch-0-mclköai2s-8ch-0-sclktxöai2s-8ch-0-sclkrxöai2s-8ch-0-lrcktxöai2s-8ch-0-lrckrxöai2s-8ch-0-sdo0ö ai2s-8ch-0-sdo1ö ai2s-8ch-0-sdo2ö ai2s-8ch-0-sdo3ö ai2s-8ch-0-sdi0ö ai2s-8ch-0-sdi1öai2s-8ch-0-sdi2öai2s-8ch-0-sdi3öai2s_8ch_1_m0i2s-8ch-1-m0-mclköai2s-8ch-1-m0-sclktxöai2s-8ch-1-m0-sclkrxöai2s-8ch-1-m0-lrcktxöai2s-8ch-1-m0-lrckrxöai2s-8ch-1-m0-sdo0öai2s-8ch-1-m0-sdo1-sdi3öai2s-8ch-1-m0-sdo2-sdi2ö ai2s-8ch-1-m0-sdo3_sdi1ö ai2s-8ch-1-m0-sdi0ö ai2s_8ch_1_m1i2s-8ch-1-m1-mclkö ai2s-8ch-1-m1-sclktxö ai2s-8ch-1-m1-sclkrxöai2s-8ch-1-m1-lrcktxöai2s-8ch-1-m1-lrckrxöai2s-8ch-1-m1-sdo0öai2s-8ch-1-m1-sdo1-sdi3öai2s-8ch-1-m1-sdo2-sdi2öai2s-8ch-1-m1-sdo3_sdi1öai2s-8ch-1-m1-sdi0öapdm_m0pdm-m0-clköapdm-m0-sdi0ö apdm-m0-sdi1ö apdm-m0-sdi2ö apdm-m0-sdi3öapdm_m1pdm-m1-clköapdm-m1-sdi0öapdm-m1-sdi1öapdm-m1-sdi2öapdm-m1-sdi3öapdm_m2pdm-m2-clkmöapdm-m2-clköapdm-m2-sdi0ö apdm-m2-sdi1öapdm-m2-sdi2öapdm-m2-sdi3öapwm0pwm0-pinö apwm0-pin-pull-downö e/4pwm1pwm1-pinöa/5pwm1-pin-pull-downöepwm2pwm2-pinöa/6pwm2-pin-pull-downöepwm3pwm3-pinöa/7pwm3-pin-pull-downöepwm4pwm4-pinöa/0pwm4-pin-pull-downöepwm5pwm5-pinöa/1pwm5-pin-pull-downöepwm6pwm6-pinöa/2pwm6-pin-pull-downöepwm7pwm7-pinöa/3pwm7-pin-pull-downöepwm8pwm8-pinö a/,pwm8-pin-pull-downö epwm9pwm9-pinö a/-pwm9-pin-pull-downö epwm10pwm10-pinö a/.pwm10-pin-pull-downö epwm11pwm11-pinöa//pwm11-pin-pull-downöertcrtc-32köa/^sdmmcsdmmc-clköf/@sdmmc-cmdög/Asdmmc-detög/Bsdmmc-pwrenöfsdmmc-bus1ögsdmmc-bus4@ögggg/Csdiosdio-clkö_/Jsdio-cmdö`/Isdio-pwrenö_sdio-wrptö_sdio-intnö_sdio-bus1ö`sdio-bus4@ö````/Hspdif_inspdif-inöaspdif_outspdif-outöa/=spi0spi0-clkög/spi0-csn0ög/ spi0-misoög/!spi0-mosiög/"spi1spi1-clkö g/#spi1-csn0ö g/$spi1-misoö g/%spi1-mosiö g/&spi1-m1spi1m1-misoögspi1m1-mosiögspi1m1-clkögspi1m1-csn0ö gspi2spi2-clkög/(spi2-csn0ög/)spi2-misoög/*spi2-mosiög/+tsadctsadc-otp-pinö atsadc-otp-outö auart0uart0-xfer öhh/uart0-ctsöauart0-rtsöauart0-rts-pinöauart1uart1-xfer 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2ethernet0mmc0mmc1mmc2device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootassigned-clocksassigned-clock-parentsclock-namesstatusinterrupt-names#phy-cellsphy-supplypinctrl-namespinctrl-0reg-shiftreg-io-widthuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiosdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesvref-supplyarm,pl330-periph-burst#dma-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplyno-sdionon-removablecap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcno-sdsd-uhs-sdr50vqmmc-supplyassigned-clock-ratesphy-moderockchip,grfclock_in_outphy-handlereset-assert-usreset-deassert-usreset-gpios#reset-cells#interrupt-cellsinterrupt-controllerrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathcolordefault-statefunctionlabellinux,default-triggerregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplyenable-active-highgpiopwmspwm-supplyregulator-init-microvoltregulator-settling-time-up-us