Ð þíˆ8(ê~ä$rockchip,rk3328-evbrockchip,rk3328 +7Rockchip RK3328 EVBaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000}/mmc@ff500000‚/mmc@ff510000‡/mmc@ff520000cpus+cpu@0Œcpuarm,cortex-a53˜œ£²ÂxÜpsciêû cpu@1Œcpuarm,cortex-a53˜œ£²ÂxÜpsciêû cpu@2Œcpuarm,cortex-a53˜œ£²ÂxÜpsciêû cpu@3Œcpuarm,cortex-a53˜œ£²ÂxÜpsciêû idle-states"pscicpu-sleeparm,idle-state/@Wxhúx„l2-cache0cacheopp-table-0operating-points-v2‰opp-408000000”Q–›~ð©œ@ºopp-600000000”#ÃF›~ð©œ@opp-816000000”0£,›B@©œ@opp-1008000000”<Ü›Èੜ@opp-1200000000”G†Œ›±(©œ@opp-1296000000”M?d›Ö ©œ@analog-soundsimple-audio-cardÆi2sßùAnalog disabledsimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0!defg, display-subsystemrockchip,display-subsystem? hdmi-soundsimple-audio-cardÆi2s߀ùHDMI disabledsimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2ãsmctimerarm,armv8-timer0!   xin24m fixed-clockERn6bxin24mBi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s˜ÿ !œ)7ui2s_clki2s_hclk�  †txrx� disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s˜ÿ !œ*8ui2s_clki2s_hclk�†txrx� disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s˜ÿ !œ+9ui2s_clki2s_hclk�†txrx� disabledspdif@ff030000rockchip,rk3328-spdif˜ÿ !œ.: umclkhclk� †tx¡default¯� disabledpdm@ff040000 rockchip,pdm˜ÿœ=Rupdm_clkpdm_hclk�†rx¡defaultsleep¯¹ disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd˜ÿ7io-domains"rockchip,rk3328-io-voltage-domain disabledgpiorockchip,rk3328-grf-gpioÃÓpower-controller!rockchip,rk3328-power-controllerß+9power-domain@6˜œDßpower-domain@5˜ œ‹BABßpower-domain@8˜œ�Fßreboot-modesyscon-reboot-modeóÈúRBÃRBÃRBà $RBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart˜ÿ !7œ&Òubaudclkapb_pclk�†txrx¡default ¯0= disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart˜ÿ !8œ'Óubaudclkapb_pclk�†txrx¡default ¯ !0= disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart˜ÿ !9œ(Ôubaudclkapb_pclk�†txrx¡default¯"0=okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c˜ÿ !$+œ7Í ui2cpclk¡default¯# disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c˜ÿ !%+œ8Î ui2cpclk¡default¯$okaypmic@18rockchip,rk805˜ %!Ebxin32krk805-clkout2ÃÓ¡default¯&Ghv'‚'Ž'š'¦(²(regulatorsDCDC_REG1 ¾vdd_logicÍ ß4å ýregulator-state-mem#;B@DCDC_REG2¾vdd_armÍ ß4å ýregulator-state-mem#;~ðDCDC_REG3¾vcc_ddrýregulator-state-mem#DCDC_REG4¾vcc_ioÍ2Z å2Z ý(regulator-state-mem#;2Z LDO_REG1¾vcc_18Íw@åw@ýregulator-state-mem#;w@LDO_REG2 ¾vcc18_emmcÍw@åw@ýregulator-state-mem#;w@LDO_REG3¾vdd_10ÍB@åB@ýregulator-state-mem#;B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c˜ÿ !&+œ9Ï ui2cpclk¡default¯) disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c˜ÿ !'+œ:Ð ui2cpclk¡default¯* disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi˜ÿ !1+œ Ñuspiclkapb_pclk� †txrx¡default¯+,-. disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt˜ÿ !(œìpwm@ff1b0000rockchip,rk3328-pwm˜ÿœ<Ö upwmpclk¡default¯/W disabledpwm@ff1b0010rockchip,rk3328-pwm˜ÿœ<Ö upwmpclk¡default¯0W disabledpwm@ff1b0020rockchip,rk3328-pwm˜ÿ œ<Ö upwmpclk¡default¯1W disabledpwm@ff1b0030rockchip,rk3328-pwm˜ÿ0 !2œ<Ö upwmpclk¡default¯2W disableddma-controller@ff1f0000arm,pl330arm,primecell˜ÿ@!bœ† uapb_pclkythermal-zonessoc-thermal„šè¨èº3tripstrip-point0ÊpÖГpassivetrip-point1ÊLÖГpassive4soc-critÊsÖÐ “criticalcooling-mapsmap0á40æ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿõtsadc@ff250000rockchip,rk3328-tsadc˜ÿ% !:$ÃPœ$Õutsadcapb_pclk¡initdefaultsleep¯5¹6'51B 8tsadc-apbD7Q† hokay3efuse@ff260000rockchip,rk3328-efuse˜ÿ&P+œ> upclk_efuse~ id@7˜cpu-leakage@17˜logic-leakage@19˜cpu-version@1a˜’Cadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc˜ÿ( !P—œ%êusaradcapb_pclk1V 8saradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-450˜ÿ0T!ZW]XY[\"©gpgpmmupppp0ppmmu0pp1ppmmu1œ‡‡ ubuscore1fiommu@ff330200rockchip,iommu˜ÿ3 !`œ“Ý uaclkiface¹ disablediommu@ff340800rockchip,iommu˜ÿ4@ !bœ�F uaclkiface¹ disabledvideo-codec@ff350000rockchip,rk3328-vpu˜ÿ5 ! ©vdpuœ�F uaclkhclkÆ8Í9iommu@ff350800rockchip,iommu˜ÿ5@ ! œ�F uaclkiface¹Í98video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec˜ÿ6€ ! œ‹BABuaxiahbcabaccore‹AB ׄׄá£Æ:Í9iommu@ff360480rockchip,iommu ˜ÿ6€@ÿ6À@ !Jœ‹B uaclkiface¹Í9:vop@ff370000rockchip,rk3328-vop˜ÿ7>ü ! œ‘x;uaclk_vopdclk_vophclk_vop1…†‡ 8axiahbdclkÆ; disabledport+ endpoint@0˜Û<Aiommu@ff373f00rockchip,iommu˜ÿ7? ! œ‘; uaclkiface¹ disabled;hdmi@ff3c0000rockchip,rk3328-dw-hdmi˜ÿ<0 !#œçFuiahbisfrcecë=ðhdmi¡default ¯>?@D7� disabledports+port@0˜endpointÛA<port@1˜codec@ff410000rockchip,rk3328-codec˜ÿAœë* upclkmclkD7� disabledphy@ff430000rockchip,rk3328-hdmi-phy˜ÿC !SœäByusysclkrefoclkrefpclk bhdmi_phyEúC cpu-version disabled=clock-controller@ff440000(rockchip,rk3328-crurockchip,crusyscon˜ÿDD7E"øx=&'(ˆ‰Ž…ƒŠŒ�ABDC"\5ˆH؉4æ$/zBBB|©€n6n6n6äáÀäáÀá£õáׄõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd˜ÿE+usb2phy@100rockchip,rk3328-usb2phy˜œBuphyclk busb480m_phyE{/DokayDotg-port$!;<=©otg-bvalidotg-idlinestateokayUhost-port !> ©linestateokayVmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc˜ÿP@ !  œ=!JNubiuciuciu-driveciu-sampleFQðÑ€okay_i{Œ¡default¯EFGH—Immc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc˜ÿQ@ !  œ>"KOubiuciuciu-driveciu-sampleFQðÑ€okay_{£°ÆJÑ¡default ¯KLMmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc˜ÿR@ ! œ?#LPubiuciuciu-driveciu-sampleFQðÑ€okay_iÑ¡default ¯NOPethernet@ff540000rockchip,rk3328-gmac˜ÿT !©macirq8œdWXZY–ßMustmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac1c 8stmmacethD7ß disabledethernet@ff550000rockchip,rk3328-gmac˜ÿUD7 !©macirq8œTSSU•ÞVIustmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy1b 8stmmacethêrmiióQßþoutputokay Rúð€e/Tmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22˜œV1d¡default¯ST*Qusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2˜ÿX !œMuotghdmi-hpd´a@cif-0dvp-d2d9-m0À´WWWWW W W WWWWWcif-1dvp-d2d9-m1À´WWWWWWWWWWWWpmicpmic-int-l´Y&sdio-pwrseqwifi-enable-h´WbchosenÂserial2:1500000n8dc-12vregulator-fixed¾dc_12výÍ·å·fsdio-pwrseqmmc-pwrseq-simple¡default¯b ÎcJsdmmc-regulatorregulator-fixed Úd¡default¯e¾vcc_sdÍ2Z å2Z ß(Ivcc-sysregulator-fixed¾vcc_sysýÍLK@åLK@ßf'vcc-phy-regulatorregulator-fixed¾vcc_phyýR compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1mmc2device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1gpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesnps,txpblphy-modephy-handleclock_in_outphy-supplyassigned-clock-ratephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathreset-gpiosgpiovin-supply