Ð þí�ß8ƒ¸( 'ƒ€radxa,rockpi-erockchip,rk3328 +7Radxa ROCK Pi Ealiases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000}/mmc@ff500000‚/mmc@ff520000cpus+cpu@0‡cpuarm,cortex-a53“—ž­½x×psciåö  cpu@1‡cpuarm,cortex-a53“—ž­½x×psciåö  cpu@2‡cpuarm,cortex-a53“—ž­½x×psciåö  cpu@3‡cpuarm,cortex-a53“—ž­½x×psciåö  idle-statespscicpu-sleeparm,idle-state*;Rxcús„l2-cache0cacheopp-table-0operating-points-v2„opp-408000000�Q––~ð¤œ@µopp-600000000�#ÃF–~ð¤œ@opp-816000000�0£,–B@¤œ@opp-1008000000�<Ü–Èज@opp-1200000000�G†Œ–±(¤œ@opp-1296000000�M?d–Ö ¤œ@analog-soundsimple-audio-cardÁi2sÚôAnalog okaysimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg' display-subsystemrockchip,display-subsystem: hdmi-soundsimple-audio-cardÁi2sÚ€ôHDMI  disabledsimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2Þsmctimerarm,armv8-timer0   xin24m fixed-clock@Mn6]xin24mDi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s“ÿ —)7pi2s_clki2s_hclk|  �txrx‹  disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s“ÿ —*8pi2s_clki2s_hclk|�txrx‹ okayi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s“ÿ —+9pi2s_clki2s_hclk|�txrx‹  disabledspdif@ff030000rockchip,rk3328-spdif“ÿ —.: pmclkhclk| �txœdefaultª‹  disabledpdm@ff040000 rockchip,pdm“ÿ—=Rppdm_clkpdm_hclk|�rxœdefaultsleepª´  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd“ÿ8io-domains"rockchip,rk3328-io-voltage-domain okay¾ËÙçõgpiorockchip,rk3328-grf-gpio/power-controller!rockchip,rk3328-power-controller;+;power-domain@6“—D;power-domain@5“ —‹BAB;power-domain@8“—�F;reboot-modesyscon-reboot-modeOÈVRBÃbRBÃpRBà €RBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart“ÿ 7—&Òpbaudclkapb_pclk|�txrxœdefault ª Œ™  disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart“ÿ 8—'Ópbaudclkapb_pclk|�txrxœdefault ª!"#Œ™  disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart“ÿ 9—(Ôpbaudclkapb_pclk|�txrxœdefaultª$Œ™ okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ $+—7Í pi2cpclkœdefaultª%  disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ %+—8Î pi2cpclkœdefaultª& okaypmic@18rockchip,rk805“ '@]xin32krk805-clkout2/œdefaultª(£ÄÒ)Þ)ê)ö))regulatorsDCDC_REG1vdd_log)=O ß4g 0Ôregulator-state-mem”¬B@DCDC_REG2vdd_arm)=O ß4g 0Ôregulator-state-mem”¬~ðDCDC_REG3vcc_ddr)=regulator-state-mem”DCDC_REG4vcc_io)=O2Z g2Z regulator-state-mem”¬2Z LDO_REG1vcc_18)=Ow@gw@9regulator-state-mem”¬w@LDO_REG2 vcc18_emmc)=Ow@gw@regulator-state-mem”¬w@LDO_REG3vdd_10)=OB@gB@regulator-state-mem”¬B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ &+—9Ï pi2cpclkœdefaultª*  disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ '+—:Ð pi2cpclkœdefaultª+  disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi“ÿ 1+— Ñpspiclkapb_pclk| �txrxœdefaultª,-./  disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt“ÿ (—ìpwm@ff1b0000rockchip,rk3328-pwm“ÿ—<Ö ppwmpclkœdefaultª0È  disabledpwm@ff1b0010rockchip,rk3328-pwm“ÿ—<Ö ppwmpclkœdefaultª1È  disabledpwm@ff1b0020rockchip,rk3328-pwm“ÿ —<Ö ppwmpclkœdefaultª2È  disabledpwm@ff1b0030rockchip,rk3328-pwm“ÿ0 2—<Ö ppwmpclkœdefaultª3È  disableddma-controller@ff1f0000arm,pl330arm,primecell“ÿ@Ó—† papb_pclkêthermal-zonessoc-thermalõ èè+4tripstrip-point0;pGÐŽpassivetrip-point1;LGÐŽpassive5soc-crit;sGÐ Žcriticalcooling-mapsmap0R50W ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿftsadc@ff250000rockchip,rk3328-tsadc“ÿ% :s$ƒÃP—$Õptsadcapb_pclkœinitdefaultsleepª6´7˜6¢B ©tsadc-apbµ8† Ù okay4efuse@ff260000rockchip,rk3328-efuse“ÿ&P+—> ppclk_efuseï id@7“cpu-leakage@17“logic-leakage@19“cpu-version@1a“Eadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc“ÿ( P—%êpsaradcapb_pclk¢V ©saradc-apb okay9egpu@ff300000"rockchip,rk3328-maliarm,mali-450“ÿ0TZW]XY[\"&gpgpmmupppp0ppmmu0pp1ppmmu1—‡‡ pbuscore¢fiommu@ff330200rockchip,iommu“ÿ3 `—“Ý paclkiface6  disablediommu@ff340800rockchip,iommu“ÿ4@ b—�F paclkiface6  disabledvideo-codec@ff350000rockchip,rk3328-vpu“ÿ5  &vdpu—�F paclkhclkC:J;iommu@ff350800rockchip,iommu“ÿ5@  —�F paclkiface6J;:video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec“ÿ6€  —‹BABpaxiahbcabaccores‹AB ƒׄׄá£C<J;iommu@ff360480rockchip,iommu “ÿ6€@ÿ6À@ J—‹B paclkiface6J;<vop@ff370000rockchip,rk3328-vop“ÿ7>ü  —‘x;paclk_vopdclk_vophclk_vop¢…†‡ ©axiahbdclkC=  disabledport+ endpoint@0“X>Ciommu@ff373f00rockchip,iommu“ÿ7?  —‘; paclkiface6  disabled=hdmi@ff3c0000rockchip,rk3328-dw-hdmi“ÿ<Œ #—çFpiahbisfrcech?mhdmiœdefault ª@ABµ8‹  disabledports+port@0“endpointXC>port@1“codec@ff410000rockchip,rk3328-codec“ÿA—ë* ppclkmclkµ8‹ okayphy@ff430000rockchip,rk3328-hdmi-phy“ÿC S—äDypsysclkrefoclkrefpclk ]hdmi_phy@wE ƒcpu-version”  disabled?clock-controller@ff440000(rockchip,rk3328-crurockchip,crusyscon“ÿDµ8@Ÿøsx=&'(ˆ‰Ž…ƒŠŒ�ABDC"\5ˆH؉4æ$¬zDDD|ƒ©€n6n6n6äáÀäáÀá£õáׄõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd“ÿE+usb2phy@100rockchip,rk3328-usb2phy“—Dpphyclk ]usb480m_phy@s{¬F okayFotg-port”$;<=&otg-bvalidotg-idlinestate  disabledXhost-port” > &linestate okayYmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc“ÿP@   —=!JNpbiuciuciu-driveciu-sampleÃÎðÑ€ okayÜæ÷œdefaultªGHIJKmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc“ÿQ@   —>"KOpbiuciuciu-driveciu-sampleÃÎðÑ€  disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc“ÿR@  —?#LPpbiuciuciu-driveciu-sampleÃÎðÑ€ okayÜ -<œdefault ªLMNJethernet@ff540000rockchip,rk3328-gmac“ÿT &macirq8—dWXZY–ßMpstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac¢c ©stmmacethµ8W okaysdf¬OObinputoPzrgmiiƒœdefaultªQŽ—¢&«mdiosnps,dwmac-mdio+ethernet-phy@1“ªRSœdefault T´'ÄÃP ÖTPethernet@ff550000rockchip,rk3328-gmac“ÿUµ8 &macirq8—TSSU•ÞVIpstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy¢b ©stmmacethzrmiioUWboutput okaymdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22“—V¢dœdefaultªVWâUusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2“ÿX —Mpotgôotgü€€@ hX musb2-phy  disabledusb@ff5c0000 generic-ehci“ÿ\  —NFhYmusb okayusb@ff5d0000 generic-ohci“ÿ]  —NFhYmusb  disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3“ÿ` C—`a„pref_clksuspend_clkbus_clkôhost ,utmi_wide5Vn�±Ê okayinterrupt-controller@ff811000 arm,gic-400ãô@“ÿ�ÿ� ÿ�@ ÿ�`   pinctrlrockchip,rk3328-pinctrlµ8+ gpio@ff210000rockchip,gpio-bank“ÿ! 3—È/ôã'gpio@ff220000rockchip,gpio-bank“ÿ" 4—É/ôãTgpio@ff230000rockchip,gpio-bank“ÿ# 5—Ê/ôãgpio@ff240000rockchip,gpio-bank“ÿ$ 6—Ë/ôãgpcfg-pull-up \pcfg-pull-down dpcfg-pull-none ,Zpcfg-pull-none-2ma , 9cpcfg-pull-up-2ma  9pcfg-pull-up-4ma  9]pcfg-pull-none-4ma , 9`pcfg-pull-down-4ma  9pcfg-pull-none-8ma , 9^pcfg-pull-up-8ma  9_pcfg-pull-none-12ma , 9 apcfg-pull-up-12ma  9 bpcfg-output-high Hpcfg-output-low Tpcfg-input-high  _[pcfg-input _i2c0i2c0-xfer lZZ%i2c1i2c1-xfer lZZ&i2c2i2c2-xfer l ZZ*i2c3i2c3-xfer lZZ+i2c3-pins lZZhdmi_i2chdmii2c-xfer lZZApdm-0pdmm0-clk lZpdmm0-fsync lZpdmm0-sdi0 lZpdmm0-sdi1 lZpdmm0-sdi2 lZpdmm0-sdi3 lZpdmm0-clk-sleep l[pdmm0-sdi0-sleep l[pdmm0-sdi1-sleep l[pdmm0-sdi2-sleep l[pdmm0-sdi3-sleep l[pdmm0-fsync-sleep l[tsadcotp-pin l Z6otp-out l Z7uart0uart0-xfer l Z\uart0-cts l Zuart0-rts l Z uart0-rts-pin l Zuart1uart1-xfer lZ\!uart1-cts lZ"uart1-rts lZ#uart1-rts-pin lZuart2-0uart2m0-xfer lZ\uart2-1uart2m1-xfer lZ\$spi0-0spi0m0-clk l\spi0m0-cs0 l \spi0m0-tx l \spi0m0-rx l \spi0m0-cs1 l \spi0-1spi0m1-clk l\spi0m1-cs0 l\spi0m1-tx l\spi0m1-rx l\spi0m1-cs1 l\spi0-2spi0m2-clk l\,spi0m2-cs0 l\/spi0m2-tx l\-spi0m2-rx l\.i2s1i2s1-mclk lZi2s1-sclk lZi2s1-lrckrx lZi2s1-lrcktx lZi2s1-sdi lZi2s1-sdo lZi2s1-sdio1 lZi2s1-sdio2 lZi2s1-sdio3 lZi2s1-sleep� l[[[[[[[[[i2s2-0i2s2m0-mclk lZi2s2m0-sclk lZi2s2m0-lrckrx lZi2s2m0-lrcktx lZi2s2m0-sdi lZi2s2m0-sdo lZi2s2m0-sleep` l[[[[[[i2s2-1i2s2m1-mclk lZi2s2m1-sclk lZi2sm1-lrckrx lZi2s2m1-lrcktx lZi2s2m1-sdi lZi2s2m1-sdo lZi2s2m1-sleepP l[[[[[spdif-0spdifm0-tx lZspdif-1spdifm1-tx lZspdif-2spdifm2-tx lZsdmmc0-0sdmmc0m0-pwren l]sdmmc0m0-pin l]sdmmc0-1sdmmc0m1-pwren l]sdmmc0m1-pin l]hsdmmc0sdmmc0-clk l^Gsdmmc0-cmd l_Hsdmmc0-dectn l]Isdmmc0-wrprt l]sdmmc0-bus1 l_sdmmc0-bus4@ l____Jsdmmc0-pins€ l]]]]]]]]sdmmc0extsdmmc0ext-clk l`sdmmc0ext-cmd l]sdmmc0ext-wrprt l]sdmmc0ext-dectn l]sdmmc0ext-bus1 l]sdmmc0ext-bus4@ l]]]]sdmmc0ext-pins€ l]]]]]]]]sdmmc1sdmmc1-clk l ^sdmmc1-cmd l _sdmmc1-pwren l_sdmmc1-wrprt l_sdmmc1-dectn l_sdmmc1-bus1 l_sdmmc1-bus4@ l____sdmmc1-pins� l ] ]]]]]]]]emmcemmc-clk laLemmc-cmd lbMemmc-pwren lZemmc-rstnout lZemmc-bus1 lbemmc-bus4@ lbbbbemmc-bus8€ lbbbbbbbbNpwm0pwm0-pin lZ0pwm1pwm1-pin lZ1pwm2pwm2-pin lZ2pwmirpwmir-pin lZ3gmac-1rgmiim1-pins` l ^ ``^``` ` `^ ^``^^^ ^`^^^^Qrmiim1-pins lcacccc c ca a Z ZZZZZgmac2phyfephyled-speed10 lZfephyled-duplex lZfephyled-rxm1 lZVfephyled-txm1 lZfephyled-linkm1 lZWtsadc_pintsadc-int l Ztsadc-pin l Zhdmi_pinhdmi-cec lZ@hdmi-hpd ldBcif-0dvp-d2d9-m0À lZZZZZ Z Z ZZZZZcif-1dvp-d2d9-m1À lZZZZZZZZZZZZephyeth-phy-int-pin ldReth-phy-reset-pin ldSledsled-pin lZfpmicpmic-int-l l\(usb3usb30-host-drv lZiwifiwifi-en lZjchosen zserial2:1500000n8adc-keys adc-keys †e ’buttons £³ðbutton-recovery ½Recovery Ãh Î'external-gmac-clock fixed-clockMsY@ ]gmac_clkin@Oleds gpio-ledsªfœdefaultled-0 è Üg îheartbeatsdmmc-regulatorregulator-fixed 'œdefaultªhvcc_sd= Kvcc-host-5v-regulatorregulator-fixed gœdefaultªi  vcc_host_5v)= )vcc-sysregulator-fixedvcc_sys)=OLK@gLK@)vcc-wifi-regulatorregulator-fixed 'œdefaultªj vcc_wifi)=  compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsvref-supplyinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpvmmc-supplycap-mmc-highspeedmmc-ddr-1_8vmmc-hs200-1_8vnon-removablevqmmc-supplysnps,txpblclock_in_outphy-handlephy-modephy-supplysnps,aalsnps,rxpbltx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltcolorlinux,default-triggergpiovin-supplyenable-active-high