Ð þíS8÷(OöÌ%google,scarlet-rev15-sku0google,scarlet-rev15google,scarlet-rev14-sku0google,scarlet-rev14google,scarlet-rev13-sku0google,scarlet-rev13google,scarlet-rev12-sku0google,scarlet-rev12google,scarlet-rev11-sku0google,scarlet-rev11google,scarlet-rev10-sku0google,scarlet-rev10google,scarlet-rev9-sku0google,scarlet-rev9google,scarlet-rev8-sku0google,scarlet-rev8google,scarlet-rev7-sku0google,scarlet-rev7google,scarlet-rev6-sku0google,scarlet-rev6google,scarlet-rev5-sku0google,scarlet-rev5google,scarletgoogle,grurockchip,rk3399 +7tabletDGoogle ScarletaliasesJ/ethernet@fe300000T/i2c@ff3c0000Y/i2c@ff110000^/i2c@ff120000c/i2c@ff130000h/i2c@ff3d0000m/i2c@ff140000r/i2c@ff150000w/i2c@ff160000|/i2c@ff3e0000�/serial@ff180000‰/serial@ff190000‘/serial@ff1a0000™/serial@ff1b0000¡/serial@ff370000©/mmc@fe320000®/mmc@fe330000cpus+cpu-mapcluster0core0³core1³core2³core3³cluster1core0³core1³cpu@0·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@1·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@2·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@3·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@100·cpuarm,cortex-a72ÃÇpsciÕè ïþ´ ( <Gthermal-idleïO'[ôcpu@101·cpuarm,cortex-a72ÃÇpsciÕè ïþ´ ( <Gthermal-idleïO'[ôidle-stateskpscicpu-sleeparm,idle-statex‰ x[ú±„G cluster-sleeparm,idle-statex‰ �[ô±ÐG display-subsystemrockchip,display-subsystemÂmemory-controllerrockchip,rk3399-dmcÈÕè¨ädmc_clkðokay(÷  ( ;ðV@o'²Z€Š'²Z€§'²Z€Ä;šÊé 7P(/pmu_a53arm,cortex-a53-pmu=pmu_a72arm,cortex-a72-pmu=psci arm,psci-1.0Îsmctimerarm,armv8-timer@=   Hxin24m fixed-clock_n6oxin24m‚G“pcie@f8000000rockchip,rk3399-pcie Ãøý�axi-baseapb-base·pci+™ª¶ èÅÄG äaclkaclk-perfhclkpm0=123ÀsyslegacyclientÐ`ãñ , pcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-38‚úúà�ûàûà8‚ƒ„…†�€(%coremgmtmgmt-stickypipepmpclkaclkðokay 1:defaultHRbr‚interrupt-controller•™Gpcie@0,0Ã+·pciwifi@0,0 qcom,ath10k(à ªGO_DUMOethernet@fe300000rockchip,rk3399-gmacÃþ0= Àmacirq8èighfjÕfMästmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macʉ %stmmacethØ å ðdisabledmmc@fe3100000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshcÃþ1@=@ððÑ€ èîMœ�äbiuciuciu-driveciu-sampleþÊy%reset ðdisabledmmc@fe3200000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshcÃþ2@=AððÑ€ Í ë èÎLš›äbiuciuciu-driveciu-sampleþÊz%resetðokay:defaultH!"#$%.8J [& do|‰–¤'°(mmc@fe330000+rockchip,rk3399-sdhci-5.1arasan,sdhci-5.1Ãþ3= ½  NðÑ€èNðäclk_xinclk_ahboemmc_cardclock‚)  phy_arasanÊÓðokay.äó G”usb@fe380000 generic-ehciÃþ8=èÈÉ*+ usb ðdisabledusb@fe3a0000 generic-ohciÃþ:=èÈÉ*+ usbðokay+bluetooth@1usbcf3,e300usb4ca,301aÃ:defaultH, &=Àwakeupusb@fe3c0000 generic-ehciÃþ<=èÊË-. usb ðdisabledusb@fe3e0000 generic-ohciÃþ>= èÊË-. usb ðdisableddebug@fe430000&arm,coresight-cpu-debugarm,primecellÃþCèM äapb_pclk³debug@fe432000&arm,coresight-cpu-debugarm,primecellÃþC èM äapb_pclk³debug@fe434000&arm,coresight-cpu-debugarm,primecellÃþC@èM äapb_pclk³debug@fe436000&arm,coresight-cpu-debugarm,primecellÃþC`èM äapb_pclk³debug@fe610000&arm,coresight-cpu-debugarm,primecellÃþaèL äapb_pclk³debug@fe710000&arm,coresight-cpu-debugarm,primecellÃþqèL äapb_pclk³usb@fe800000rockchip,rk3399-dwc3+0è�ƒöøôùGäref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk% %usb3-otgðokay/usb@fe800000 snps,dwc3Ãþ€=iè�öƒärefbus_earlysuspend"host01 usb2-phyusb3-phy *utmi_wide3Kl…¦Êðokayusb@fe900000rockchip,rk3399-dwc3+0è‚„÷øôùGäref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk& %usb3-otg ðdisabledusb@fe900000 snps,dwc3Ãþ�=nè‚÷„ärefbus_earlysuspend"otg23 usb2-phyusb3-phy *utmi_wide3Kl…¦Ê ðdisableddp@fec00000rockchip,rk3399-cdn-dpÃþÀ=  r¡õá ë èru¡oäcore-clkpclkspdifgrf4Ê HJý%spdifdptxapbcoreØ Èðokay/GÛportsport+endpoint@0ÃÙ5G£endpoint@1ÃÙ6G�interrupt-controller@fee00000 arm,gic-v3™+•PÃþàþð ÿðÿñÿò= Ginterrupt-controller@fee20000arm,gic-v3-itséøÃþâGppi-partitionsinterrupt-partition-0Ginterrupt-partition-1Gsaradc@ff100000rockchip,rk3399-saradcÃÿ=> èPeäsaradcapb_pclkÔ %saradc-apb ðdisabledi2c@ff110000rockchip,rk3399-i2cÃÿ A ëÂèAU äi2cpclk=;:defaultH7+ ðdisabledi2c@ff120000rockchip,rk3399-i2cÃÿ B ëÂèBV äi2cpclk=#:defaultH8+ðokay_€26,digitizer@9 hid-over-i2cà  &=M:defaultH9:i2c@ff130000rockchip,rk3399-i2cÃÿ C ëÂèCW äi2cpclk=":defaultH;+ðokay_€26,touchscreen@10elan,ekth3500à &=:defaultH<= \ i2c@ff140000rockchip,rk3399-i2cÃÿ D ëÂèDX äi2cpclk=&:defaultH>+ ðdisabledi2c@ff150000rockchip,rk3399-i2cÃÿ E ëÂèEY äi2cpclk=%:defaultH?+ ðdisabledi2c@ff160000rockchip,rk3399-i2cÃÿ F ëÂèFZ äi2cpclk=$:defaultH@A+ðokay_€26,camera@36 ovti,ov5695Ã6:defaultHBè©äxvclkhCtD€ \EportendpointÙF�G¦camera@3c ovti,ov2685Ã<:defaultHGè©äxvclkhC€t \EportendpointÙH�G§serial@ff180000&rockchip,rk3399-uartsnps,dw-apb-uartÃÿèQ`äbaudclkapb_pclk=c˜¢:defaultHI ðdisabledserial@ff190000&rockchip,rk3399-uartsnps,dw-apb-uartÃÿèRaäbaudclkapb_pclk=b˜¢:defaultHJ ðdisabledserial@ff1a0000&rockchip,rk3399-uartsnps,dw-apb-uartÃÿèSbäbaudclkapb_pclk=d˜¢:defaultHKðokayserial@ff1b0000&rockchip,rk3399-uartsnps,dw-apb-uartÃÿèTcäbaudclkapb_pclk=e˜¢:defaultHL ðdisabledspi@ff1c0000(rockchip,rk3399-spirockchip,rk3066-spiÃÿèG[äspiclkapb_pclk=D¯M M ´txrx:defaultHNOPQ+ ðdisabledspi@ff1d0000(rockchip,rk3399-spirockchip,rk3066-spiÃÿèH\äspiclkapb_pclk=5¯M M ´txrx:defaultsleepHRSTU+ðokay¾Vflash@0jedec,spi-norÃȘ–€spi@ff1e0000(rockchip,rk3399-spirockchip,rk3066-spiÃÿèI]äspiclkapb_pclk=4¯MM´txrx:defaultHWXYZ+ðokaycr50@0 google,cr50à &=:defaultH[È 5spi@ff1f0000(rockchip,rk3399-spirockchip,rk3066-spiÃÿèJ^äspiclkapb_pclk=C¯MM´txrx:defaultH\]^_+ ðdisabledspi@ff200000(rockchip,rk3399-spirockchip,rk3066-spiÃÿ èK_äspiclkapb_pclk=„¯`` ´txrx:defaultHabcdÊ+ðokayec@0google,cros-ec-spià &=:defaultHeÈ-ÆÀi2c-tunnelgoogle,cros-ec-i2c-tunnelÚ+sbs-battery@bsbs,sbs-batteryà ìextcon0google,extcon-usbc-cros-ecG/keyboard-controllergoogle,cros-ec-keyb(8 KDe;<=>?@A B CD}0Y1 d"#(  \V |})  Ž + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ithermal-zonescpu-thermalrdˆè–ftripscpu_alert0¦Ð²Ð?passiveGgcpu_alert1¦X²Ð?passiveGhcpu_crit¦s²Ð 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:syscon@ff320000)rockchip,rk3399-pmugrfsysconsimple-mfdÃÿ2Gio-domains&rockchip,rk3399-pmu-io-voltage-domainðokay Uspi@ff350000(rockchip,rk3399-spirockchip,rk3066-spiÃÿ5è‚‚äspiclkapb_pclk=<:defaultHƒ„…†+ ðdisabledserial@ff370000&rockchip,rk3399-uartsnps,dw-apb-uartÃÿ7è‚‚"äbaudclkapb_pclk=f˜¢:defaultH‡ ðdisabledi2c@ff3c0000rockchip,rk3399-i2cÃÿ< ‚  ëÂè‚ ‚ äi2cpclk=9:defaultHˆ+ ðdisabledi2c@ff3d0000rockchip,rk3399-i2cÃÿ= ‚  ëÂè‚ ‚ äi2cpclk=8:defaultH‰+ ðdisabledi2c@ff3e0000rockchip,rk3399-i2cÃÿ> ‚  ëÂè‚ ‚ äi2cpclk=::defaultHŠ+ðokay_€26,da7219@1a dlg,da7219à &=èYämclk d ( tdiff:defaultH‹ ‡ ’Œ  GÚda7219_aad ­ ¾ Ê2 Öô æ ÷32ms_64ms    * :! J>pwm@ff420000(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB \:defaultH�è‚ðokayGÐpwm@ff420010(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB \:defaultHŽè‚ðokayGåpwm@ff420020(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB  \:defaultH�è‚ðokayGÎpwm@ff420030(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB0 \:defaultH�è‚ðokayGÌdfi@ff630000Ãÿc@rockchip,rk3399-dfiÈ=ƒèy äpclk_ddr_monðokayGvideo-codec@ff650000rockchip,rk3399-vpuÃÿe =rq Àvepuvdpuèëê äaclkhclk g‘Êiommu@ff650800rockchip,iommuÃÿe@=sèëê äaclkiface nÊG‘video-codec@ff660000rockchip,rk3399-vdecÃÿf€=t èí쟞äaxiahbcabaccore g’Ê iommu@ff660480rockchip,iommu Ãÿf€@ÿfÀ@=uèíì äaclkifaceÊ  nG’iommu@ff670800rockchip,iommuÃÿg@=*èáÝ äaclkiface n ðdisabledrga@ff680000rockchip,rk3399-rgaÃÿh=7èÜåmäaclkhclksclkjgi %coreaxiahbÊ!efuse@ff690000rockchip,rk3399-efuseÃÿi€+è} äpclk_efusecpu-id@7Ãcpu-leakage@17Ãgpu-leakage@18Ãcenter-leakage@19Ãcpu-leakage@1aÃlogic-leakage@1bÃwafer-info@1cÃdma-controller@ff6d0000arm,pl330arm,primecellÃÿm@ = { †èÓ äapb_pclkG`dma-controller@ff6e0000arm,pl330arm,primecellÃÿn@ = { †èÔ äapb_pclkGMclock-controller@ff750000rockchip,rk3399-pmucruÃÿuè“äxin24mØ‚ � ‚(JñG‚clock-controller@ff760000rockchip,rk3399-cruÃÿvè“äxin24mØ ‚ �ˆ ÀÀ@ÂÁBÉÂCãxÞíD#ÃF_^;šÊðÑ€xhÀ<4`õáõáúð€/¯õáúð€ׄ ë ëÂׄׄGsyscon@ff770000&rockchip,rk3399-grfsysconsimple-mfdÃÿw+G io-domains"rockchip,rk3399-io-voltage-domainðokay ª · Ä Ô(mipi-dphy-rx0rockchip,rk3399-mipi-dphy-rx0èw¥oädphy-refdphy-cfggrfÊ áðokayG¥usb2phy@e450rockchip,rk3399-usb2phyÃäPè{äphyclk‚oclk_usbphy0_480mðokayG*host-port á= ÀlinestateðokayG+otg-port á0=ghjÀotg-bvalidotg-idlinestateðokayG0usb2phy@e460rockchip,rk3399-usb2phyÃä`è|äphyclk‚oclk_usbphy1_480m ðdisabledG-host-port á= ÀlinestateðokayG.otg-port á0=lmoÀotg-bvalidotg-idlinestateðokayG2phy@f780rockchip,rk3399-emmc-phyÃ÷€$è”äemmcclk ì2 áðokayG)pcie-phyrockchip,rk3399-pcie-phyèŠärefclk á‡%phyðokayGphy@ff7c0000rockchip,rk3399-typec-phyÃÿ|è~}ätcpdcoretcpdphy-ref ~úð€Ê•”L%uphyuphy-pipeuphy-tcphyØ ðokay/dp-port áG4usb3-port áG1phy@ff800000rockchip,rk3399-typec-phyÃÿ€è€ätcpdcoretcpdphy-ref €úð€Ê �œM%uphyuphy-pipeuphy-tcphyØ  ðdisableddp-port áusb3-port áG3watchdog@ff848000 rockchip,rk3399-wdtsnps,dw-wdtÃÿ„€è|=xrktimer@ff850000rockchip,rk3399-timerÃÿ…=QèhZ äpclktimerspdif@ff870000rockchip,rk3399-spdifÃÿ‡=B¯`´tx ämclkhclkèU×ÊÈðokayG×i2s@ff880000(rockchip,rk3399-i2srockchip,rk3066-i2sÃÿˆØ ='¯``´txrxäi2s_clki2s_hclkèVÔ:bclk_onbclk_offH•¾–ÊÈðokayGÖi2s@ff890000(rockchip,rk3399-i2srockchip,rk3066-i2sÃÿ‰=(¯``´txrxäi2s_clki2s_hclkèWÕ:defaultH—ÊÈ ðdisabledi2s@ff8a0000(rockchip,rk3399-i2srockchip,rk3066-i2sÃÿŠ=)¯``´txrxäi2s_clki2s_hclkèXÖÊÈ ðdisabledGªvop@ff8f0000rockchip,rk3399-vop-lit Ãÿ� ÿ� =w ÛÛׄõáèÛµÛäaclk_vopdclk_vophclk_vop g˜Ê %axiahbdclkðokayport+Gendpoint@0ÃÙ™G¯endpoint@1ÃÙšG½endpoint@2ÃÙ›G­endpoint@3ÃÙœG¹endpoint@4ÃÙ�G6iommu@ff8f3f00rockchip,iommuÃÿ�?=wèÛÛ äaclkifaceÊ nðokayG˜vop@ff900000rockchip,rk3399-vop-big Ãÿ� ÿ� =v ÙÙׄõáèÙ´Ùäaclk_vopdclk_vophclk_vop gžÊ %axiahbdclkðokayport+Gendpoint@0ÃÙŸG¼endpoint@1ÃÙ G®endpoint@2ÃÙ¡G¬endpoint@3ÃÙ¢G¸endpoint@4ÃÙ£G5iommu@ff903f00rockchip,iommuÃÿ�?=vèÙÙ äaclkifaceÊ nðokayGžisp0@ff910000rockchip,rk3399-cif-ispÃÿ‘@=+ènéãäispaclkhclk g¤¥ dphyÊðokayports+port@0Ã+endpoint@0ÃÙ¦�GFendpoint@1ÃÙ§�GHiommu@ff914000rockchip,iommu Ãÿ‘@ÿ‘P=+èéã äaclkiface nÊ ðokayG¤isp1@ff920000rockchip,rk3399-cif-ispÃÿ’@=,èoêääispaclkhclk g¨© dphyÊ ðdisabledports+port@0Ã+iommu@ff924000rockchip,iommu Ãÿ’@ÿ’P=,èêä äaclkiface nÊ G¨hdmi-soundsimple-audio-card i2s 4 Nhdmi-sound ðdisabledsimple-audio-card,cpu eªsimple-audio-card,codec e«hdmi@ff940000rockchip,rk3399-dw-hdmiÃÿ”¢=(ètqpoäiahbisfrcecgrfrefÊØ È ðdisabledG«ports+port@0Ã+endpoint@0ÃÙ¬G¡endpoint@1ÃÙ­G›port@1Ãmipi@ff960000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsiÃÿ–€=- è¢p£oärefpclkphy_cfggrfÊû%apbØ +ðokay oports+port@0Ã+endpoint@0ÃÙ®G endpoint@1ÃÙ¯G™port@1ÃendpointÙ°G¶panel@0à |± †²:defaultH³innolux,p097pfgh´ “µports+port@0ÃendpointÙ¶G°port@1Ãendpoint@1Ù·Gºmipi@ff968000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsiÃÿ–€€=. è¢q¤oärefpclkphy_cfggrfÊü%apbØ + áðokayG©ports+port@0Ã+endpoint@0ÃÙ¸G¢endpoint@1ÃÙ¹Gœport@1ÃendpointÙºG·edp@ff970000rockchip,rk3399-edpÃÿ—€= èjlo ädppclkgrf:defaultH»Ê%dpØ  ðdisabledports+port@0Ã+endpoint@0ÃÙ¼GŸendpoint@1ÃÙ½Gšgpu@ff9a0000#rockchip,rk3399-maliarm,mali-t860Ãÿš0= ÀjobmmugpuèÐïÊ#ðokay(¾ Ÿ¿Gjpinctrlrockchip,rk3399-pinctrlØ È+:default HÀÁÂgpio@ff720000rockchip,gpio-bankÃÿrè‚= « »•™â ÇCLK_32K_APEC_IN_RW_ODSPK_PA_ENWLAN_PERST_1V8_LWLAN_PD_1V8_LWLAN_RF_KILL_1V8_LBIGCPU_DVS_PWMSD_CD_L_JTAG_ENBT_EN_BT_RF_KILL_1V8_LPMUIO2_33_18_L_PP3300_S0_ENTOUCH_RESET_LAP_EC_WARM_RESET_REQPEN_RESET_LAP_FLASH_WP_LGgpio@ff730000rockchip,gpio-bankÃÿsè‚= « »•™‰ ÇPEN_INT_ODLPEN_EJECT_ODLBT_HOST_WAKE_1V8_LWLAN_HOST_WAKE_1V8_LTOUCH_INT_ODLAP_EC_S3_S0_LAP_EC_OVERTEMPAP_SPI_FLASH_MISOAP_SPI_FLASH_MOSI_RAP_SPI_FLASH_CLK_RAP_SPI_FLASH_CS_L_RSD_CARD_DET_ODLAP_EXPANSION_IO1AP_EXPANSION_IO2AP_I2C_DISP_SDAAP_I2C_DISP_SCLH1_INT_ODLEC_AP_INT_ODLLITCPU_DVS_PWMAP_I2C_AUDIO_SDAAP_I2C_AUDIO_SCLAP_EXPANSION_IO3HEADSET_INT_ODLAP_EXPANSION_IO4G&gpio@ff780000rockchip,gpio-bankÃÿxèP= « »•™  ÇAP_I2C_PEN_SDAAP_I2C_PEN_SCLSD_IO_PWR_ENUCAM_RST_LPP1250_CAM_ENWCAM_RST_LAP_EXPANSION_IO5AP_I2C_CAM_SDAAP_I2C_CAM_SCLAP_H1_SPI_MISOAP_H1_SPI_MOSIAP_H1_SPI_CLKAP_H1_SPI_CS_LUART_EXPANSION_TX_AP_RXUART_AP_TX_EXPANSION_RXUART_EXPANSION_RTS_AP_CTSUART_AP_RTS_EXPANSION_CTSAP_SPI_EC_MISOAP_SPI_EC_MOSIAP_SPI_EC_CLKAP_SPI_EC_CS_LPP2800_CAM_ENCLK_24M_CAMWLAN_PCIE_CLKREQ_1V8_LSD_PWR_3000_1800_LGEgpio@ff788000rockchip,gpio-bankÃÿx€èQ= « »•™‚ ÇI2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDI_0STRAP_LCDBIAS_LSTRAP_FEATURE_1STRAP_FEATURE_2I2S0_SDO_0gpio@ff790000rockchip,gpio-bankÃÿyèR= « »•™Ü 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d ™ ­ ¿ =J ×NGÏppvar-litcpuvctrl-regulator Šppvar_litcpu ¿ =J ×N 1Ï = =JN P€G ppvar-gpu-pwmpwm-regulator Šppvar_gpu_pwm úÐ  ÿË d d ™ ­ ¿ 3p ×ÇPGÑppvar-gpuvctrl-regulator Šppvar_gpu ¿ 3p ×ÇP 1Ñ = 3pÇP P†G¿pp900-appp3000-sd-slotregulator-fixed Špp3000_sd_slot:defaultHÒ n �² ïŒG'ppvar-sd-card-ioregulator-gpio Šppvar_sd_card_io:defaultHÓÔ n †E 4E!w@2Z  ¿w@ ×2Z G(pp3300-trackpadap-rtc-clk fixed-clock_€oxin32k‚max98357amaxim,max98357a:defaultHÕ ’ ŸÈðokayGØsoundrockchip,rk3399-gru-sound ¬Ö× ¹ØÙÚÛpp1250-s3regulator-fixed Špp1250_s3 ™ ­ ¿Ð ×Ð ïËGÝpp1250-dvddregulator-fixed Špp1250_dvdd:defaultHÜ n �E Èè ïÝGDpp900-s0regulator-fixed Špp900_s0 ™ ­ ¿ »  × »  ïËGppvarn-lcdregulator-fixed Šppvarn_lcd:defaultHÞ n �² ïËGµppvarp-lcdregulator-fixed Šppvarp_lcd:defaultHß n �² ïËG´pp900-s3regulator-fixed Špp900_s3 ™ ­ ¿ »  × »  ïpp2800-avddregulator-fixed Špp2800_avdd:defaultHà n �E Èd ïŒGCbt-3v3regulator-fixed Šbt_3v3:defaultHá n � ïŒGãwlan-3v3regulator-fixed Šwlan_3v3:defaultHâ n � Ù' ïãGbacklightpwm-backlight †²:defaultHä úåB@ õ'G±dmic dmic-codec ²:defaultHæúGÙgpio-keys gpio-keys:defaultHçswitch-pen-insert Pen Insert 4&%0A compatibleinterrupt-parent#address-cells#size-cellschassis-typemodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4mmc0mmc1cpudevice_typeregenable-methodcapacity-dmips-mhzclocks#cooling-cellsdynamic-power-coefficientcpu-idle-statesoperating-points-v2cpu-supplyphandleduration-usexit-latency-usentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usmin-residency-usportsrockchip,pmudevfreq-eventsclock-namesstatusrockchip,pd-idle-nsrockchip,sr-idle-nsrockchip,sr-mc-gate-idle-nsrockchip,srpd-lite-idle-nsrockchip,standby-idle-nsrockchip,ddr3_odt_dis_freqrockchip,lpddr3_odt_dis_freqrockchip,lpddr4_odt_dis_freqrockchip,sr-mc-gate-idle-dis-freq-hzrockchip,srpd-lite-idle-dis-freq-hzrockchip,standby-idle-dis-freq-hzcenter-supplyinterruptsarm,no-tick-in-suspendclock-frequencyclock-output-names#clock-cellsreg-names#interrupt-cellsaspm-no-l0sbus-rangeinterrupt-namesinterrupt-map-maskinterrupt-mapmax-link-speedmsi-mapphysphy-namesrangesresetsreset-namesep-gpiospinctrl-namespinctrl-0vpcie3v3-supplyvpcie1v8-supplyvpcie0v9-supplypcie-reset-suspendinterrupt-controllerqcom,ath10k-calibration-variantpower-domainsrockchip,grfsnps,txpblmax-frequencyfifo-depthassigned-clocksassigned-clock-ratesbus-widthcap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplyarasan,soc-ctl-syscondisable-cqe-dcmdmmc-hs400-1_8vmmc-hs400-enhanced-strobenon-removableextcondr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirk#sound-dai-cellsremote-endpointmsi-controller#msi-cellsaffinity#io-channel-cellsi2c-scl-falling-time-nsi2c-scl-rising-time-nshid-descr-addrreset-gpiosavdd-supplydvdd-supplydovdd-supplydata-lanesreg-shiftreg-io-widthdmasdma-namespinctrl-1spi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countgoogle,usb-port-idkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymappolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#power-domain-cellspm_qospmu1830-supplydlg,micbias-lvldlg,mic-amp-in-selVDD-supplyVDDMIC-supplyVDDIO-supplydlg,adc-1bit-rptdlg,btn-avgdlg,btn-cfgdlg,mic-det-thrdlg,jack-ins-debdlg,jack-det-ratedlg,jack-rem-debdlg,a-d-btn-thrdlg,d-b-btn-thrdlg,b-c-btn-thrdlg,c-mic-btn-thr#pwm-cellsiommus#iommu-cells#dma-cellsarm,pl330-periph-burst#reset-cellsaudio-supplybt656-supplygpio1830-supplysdmmc-supply#phy-cellsdrive-impedance-ohmrockchip,disable-mmu-resetsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namesound-daiclock-masterbacklightenable-gpiosavee-supplymali-supplygpio-controller#gpio-cellsgpio-line-namesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplypwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitctrl-supplyctrl-voltage-rangeregulator-settling-time-up-usenable-active-highgpioenable-gpiosdmode-gpiossdmode-delayrockchip,cpurockchip,codecstartup-delay-usregulator-enable-ramp-delaypwm-delay-usdmicen-gpioswakeup-delay-mslabellinux,codelinux,input-typewakeup-source