Ð þíÙq8Ϥ( ÍÏl%pine64,pinephone-prorockchip,rk3399 +7Pine64 PinePhonePro=handsetaliasesJ/ethernet@fe300000T/i2c@ff3c0000Y/i2c@ff110000^/i2c@ff120000c/i2c@ff130000h/i2c@ff3d0000m/i2c@ff140000r/i2c@ff150000w/i2c@ff160000|/i2c@ff3e0000�/serial@ff180000‰/serial@ff190000‘/serial@ff1a0000™/serial@ff1b0000¡/serial@ff370000©/mmc@fe310000®/mmc@fe320000³/mmc@fe330000cpus+cpu-mapcluster0core0¸core1¸core2¸core3¸cluster1core0¸core1¸cpu@0¼cpuarm,cortex-a53ÈÌpsciÚåíôd - A Lcpu@1¼cpuarm,cortex-a53ÈÌpsciÚåíôd - A Lcpu@2¼cpuarm,cortex-a53ÈÌpsciÚåíôd - A Lcpu@3¼cpuarm,cortex-a53ÈÌpsciÚåíôd - A Lcpu@100¼cpuarm,cortex-a72ÈÌpsciÚí ô´ - ALthermal-idleôT'`ôcpu@101¼cpuarm,cortex-a72ÈÌpsciÚí ô´ - ALthermal-idleôT'`ôidle-statesppscicpu-sleeparm,idle-state}Ž¥x`ú¶„L cluster-sleeparm,idle-state}Ž¥�`ô¶ÐL display-subsystemrockchip,display-subsystemÇmemory-controllerrockchip,rk3399-dmcÍÚí¨édmc_clk õdisabledpmu_a53arm,cortex-a53-pmuüpmu_a72arm,cortex-a72-pmuüpsci arm,psci-1.0Ósmctimerarm,armv8-timer@ü   xin24m fixed-clockn6.xin24mALpcie@f8000000rockchip,rk3399-pcie ÈøýNaxi-baseapb-base¼pci+Xiu íÅÄG éaclkaclk-perfhclkpm0ü123syslegacyclient�`¢°¿ Ç,Ìpcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-38Ö‚úúà�ûàûà8Ý‚ƒ„…†�€(äcoremgmtmgmt-stickypipepmpclkaclk õdisabledinterrupt-controllerðXLethernet@fe300000rockchip,rk3399-gmacÈþ0ü macirq8íighfjÕfMéstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac݉ ästmmaceth  õdisabledmmc@fe3100000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshcÈþ1@ü@+ðÑ€ íîMœ�ébiuciuciu-driveciu-sample9Ýyäreset õdisabledmmc@fe3200000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshcÈþ2@üA+ðÑ€DÍT ë íÎLš›ébiuciuciu-driveciu-sample9Ýzäresetõokayis „�˜default¦°¼ mmc@fe330000+rockchip,rk3399-sdhci-5.1arasan,sdhci-5.1Èþ3ü ÉDNT ëÂíNðéclk_xinclk_ahb.emmc_cardclockAÇ! Ìphy_arasanßõokayiðÿLƒusb@fe380000 generic-ehciÈþ8üíÈÉ"Ç#Ìusb õdisabledusb@fe3a0000 generic-ohciÈþ:üíÈÉ"Ç#Ìusb õdisabledusb@fe3c0000 generic-ehciÈþ<üíÊË$Ç%Ìusb õdisabledusb@fe3e0000 generic-ohciÈþ>ü íÊË$Ç%Ìusb õdisableddebug@fe430000&arm,coresight-cpu-debugarm,primecellÈþCíM éapb_pclk¸debug@fe432000&arm,coresight-cpu-debugarm,primecellÈþC íM éapb_pclk¸debug@fe434000&arm,coresight-cpu-debugarm,primecellÈþC@íM éapb_pclk¸debug@fe436000&arm,coresight-cpu-debugarm,primecellÈþC`íM éapb_pclk¸debug@fe610000&arm,coresight-cpu-debugarm,primecellÈþaíL éapb_pclk¸debug@fe710000&arm,coresight-cpu-debugarm,primecellÈþqíL éapb_pclk¸usb@fe800000rockchip,rk3399-dwc3+Ö0í�ƒöøôùGéref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clkÝ% äusb3-otg õdisabledusb@fe800000 snps,dwc3Èþ€üií�öƒérefbus_earlysuspend otgÇ&'Ìusb2-phyusb3-phy utmi_wide6Wp‘ õdisabledusb@fe900000rockchip,rk3399-dwc3+Ö0í‚„÷øôùGéref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clkÝ& äusb3-otg õdisabledusb@fe900000 snps,dwc3Èþ�üní‚÷„érefbus_earlysuspend otgÇ()Ìusb2-phyusb3-phy utmi_wide6Wp‘ õdisableddp@fec00000rockchip,rk3399-cdn-dpÈþÀü Dr¡Tõá ë íru¡oécore-clkpclkspdifgrfÇ*+ ÝHJýäspdifdptxapbcore³ õdisabledportsport+endpoint@0ÈÄ,L“endpoint@1ÈÄ-L�interrupt-controller@fee00000 arm,gic-v3X+ÖðPÈþàþð ÿðÿñÿòü Linterrupt-controller@fee20000arm,gic-v3-itsÔãÈþâLppi-partitionsinterrupt-partition-0îLinterrupt-partition-1îLsaradc@ff100000rockchip,rk3399-saradcÈÿü>÷íPeésaradcapb_pclkÝÔ äsaradc-apb õdisabledi2c@ff110000rockchip,rk3399-i2cÈÿDAT ëÂíAU éi2cpclkü;˜default¦.+ õdisabledi2c@ff120000rockchip,rk3399-i2cÈÿDBT ëÂíBV éi2cpclkü#˜default¦/+ õdisabledi2c@ff130000rockchip,rk3399-i2cÈÿDCT ëÂíCW éi2cpclkü"˜default¦0+ õdisabledi2c@ff140000rockchip,rk3399-i2cÈÿDDT ëÂíDX éi2cpclkü&˜default¦1+ õdisabledi2c@ff150000rockchip,rk3399-i2cÈÿDET ëÂíEY éi2cpclkü%˜default¦2+ õdisabledi2c@ff160000rockchip,rk3399-i2cÈÿDFT ëÂíFZ éi2cpclkü$˜default¦3+ õdisabledserial@ff180000&rockchip,rk3399-uartsnps,dw-apb-uartÈÿíQ`ébaudclkapb_pclküc ˜default¦4 õdisabledserial@ff190000&rockchip,rk3399-uartsnps,dw-apb-uartÈÿíRaébaudclkapb_pclküb ˜default¦5 õdisabledserial@ff1a0000&rockchip,rk3399-uartsnps,dw-apb-uartÈÿíSbébaudclkapb_pclküd ˜default¦6õokayserial@ff1b0000&rockchip,rk3399-uartsnps,dw-apb-uartÈÿíTcébaudclkapb_pclküe ˜default¦7 õdisabledspi@ff1c0000(rockchip,rk3399-spirockchip,rk3066-spiÈÿíG[éspiclkapb_pclküD 8 8 %txrx˜default¦9:;<+ õdisabledspi@ff1d0000(rockchip,rk3399-spirockchip,rk3066-spiÈÿíH\éspiclkapb_pclkü5 8 8 %txrx˜default¦=>?@+ õdisabledspi@ff1e0000(rockchip,rk3399-spirockchip,rk3066-spiÈÿíI]éspiclkapb_pclkü4 88%txrx˜default¦ABCD+ õdisabledspi@ff1f0000(rockchip,rk3399-spirockchip,rk3066-spiÈÿíJ^éspiclkapb_pclküC 88%txrx˜default¦EFGH+ õdisabledspi@ff200000(rockchip,rk3399-spirockchip,rk3066-spiÈÿ íK_éspiclkapb_pclkü„ II %txrx˜default¦JKLM+ õdisabledthermal-zonescpu-thermal/dEèSNtripscpu_alert0cýèoÐEpassiveLOcpu_alert1c  oÐEpassiveLPcpu_critcsoÐ Ecriticalcooling-mapsmap0zOÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1zPHÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿgpu-thermal/dEèSNtripsgpu_alert0c$øoÐEpassiveLQgpu_critcsoÐ Ecriticalcooling-mapsmap0zQ Rÿÿÿÿÿÿÿÿtsadc@ff260000rockchip,rk3399-tsadcÈÿ&üaDOT q°íOdétsadcapb_pclkÝè ätsadc-apbŽs˜initdefaultsleep¦S¥T¯S¹õokayÏæLNqos@ffa58000rockchip,rk3399-qossysconÈÿ¥€ L\qos@ffa5c000rockchip,rk3399-qossysconÈÿ¥À L]qos@ffa60080rockchip,rk3399-qossysconÈÿ¦€ qos@ffa60100rockchip,rk3399-qossysconÈÿ¦ qos@ffa60180rockchip,rk3399-qossysconÈÿ¦€ qos@ffa70000rockchip,rk3399-qossysconÈÿ§ L`qos@ffa70080rockchip,rk3399-qossysconÈÿ§€ Laqos@ffa74000rockchip,rk3399-qossysconÈÿ§@ L^qos@ffa76000rockchip,rk3399-qossysconÈÿ§` L_qos@ffa90000rockchip,rk3399-qossysconÈÿ© Lbqos@ffa98000rockchip,rk3399-qossysconÈÿ©€ LUqos@ffaa0000rockchip,rk3399-qossysconÈÿª Lcqos@ffaa0080rockchip,rk3399-qossysconÈÿª€ Ldqos@ffaa8000rockchip,rk3399-qossysconÈÿª€ Leqos@ffaa8080rockchip,rk3399-qossysconÈÿª€€ Lfqos@ffab0000rockchip,rk3399-qossysconÈÿ« LVqos@ffab0080rockchip,rk3399-qossysconÈÿ«€ LWqos@ffab8000rockchip,rk3399-qossysconÈÿ«€ LXqos@ffac0000rockchip,rk3399-qossysconÈÿ¬ LYqos@ffac0080rockchip,rk3399-qossysconÈÿ¬€ LZqos@ffac8000rockchip,rk3399-qossysconÈÿ¬€ Lgqos@ffac8080rockchip,rk3399-qossysconÈÿ¬€€ Lhqos@ffad0000rockchip,rk3399-qossysconÈÿ­ Liqos@ffad8080rockchip,rk3399-qossysconÈÿ­€€ qos@ffae0000rockchip,rk3399-qossysconÈÿ® L[power-management@ff310000&rockchip,rk3399-pmusysconsimple-mfdÈÿ1power-controller!rockchip,rk3399-power-controller+Lpower-domain@34È"íáÝUpower-domain@33È!íÜåVWpower-domain@31ÈíëêXpower-domain@32È  íí쟞YZpower-domain@35È#íÐ[power-domain@25Èílpower-domain@23Èíð\power-domain@22ÈíÕf]power-domain@27ÈíÎL^power-domain@28Èíî_power-domain@8Èí~}power-domain@9È í€power-domain@24Èíô`apower-domain@15È+power-domain@21ÈíÞçrbpower-domain@19Èíåßcdpower-domain@20Èíæàefpower-domain@16È+power-domain@17ÈíÙÙghpower-domain@18ÈíÛÛisyscon@ff320000)rockchip,rk3399-pmugrfsysconsimple-mfdÈÿ2Lio-domains&rockchip,rk3399-pmu-io-voltage-domainõokayjspi@ff350000(rockchip,rk3399-spirockchip,rk3066-spiÈÿ5íkkéspiclkapb_pclkü<˜default¦lmno+ õdisabledserial@ff370000&rockchip,rk3399-uartsnps,dw-apb-uartÈÿ7íkk"ébaudclkapb_pclküf ˜default¦p õdisabledi2c@ff3c0000rockchip,rk3399-i2cÈÿ<Dk T ëÂík k éi2cpclkü9˜default¦q+õokay€+¨Bpmic@1crockchip,rk818È rüA.xin32krk808-clkout2˜default¦sZ{‰t•t¡t­t¹tÅÑtÝregulatorsDCDC_REG1 évdd_cpu_lø  Yø6à˜NqL regulator-state-memcDCDC_REG2 évdd_centerø  56B@Nqregulator-state-memcDCDC_REG3évcc_ddrø regulator-state-mem|DCDC_REG4évcc_1v8ø w@6w@Ljregulator-state-mem|LDO_REG1évcca3v0_codec-ÆÀ6-ÆÀLDO_REG2 évcc3v0_touch-ÆÀ6-ÆÀLDO_REG3évcca1v8_codecw@6w@L�LDO_REG4 érk818_pwr_onø 2Z 62Z regulator-state-mem|LDO_REG5évcc_3v0ø -ÆÀ6-ÆÀL‚regulator-state-mem|LDO_REG6évcc_1v5ø ã`6ã`regulator-state-mem|LDO_REG7 évcc1v8_dvpw@6w@L€LDO_REG8 évcc3v3_s3ø 2Z 62Z regulator-state-memcLDO_REG9 évccio_sdw@62Z L SWITCH_REG évcc3v3_s0ø regulator-state-mem|regulator@40silergy,syr827È@”˜default¦u évdd_cpu_b Yø6Œ0Nèø Lregulator-state-memcregulator@41silergy,syr828ÈA”˜default¦vévdd_gpu Yø6à˜Nèø regulator-state-memci2c@ff3d0000rockchip,rk3399-i2cÈÿ=Dk T ëÂík k éi2cpclkü8˜default¦w+ õdisabledi2c@ff3e0000rockchip,rk3399-i2cÈÿ>Dk T ëÂík k éi2cpclkü:˜default¦x+ õdisabledpwm@ff420000(rockchip,rk3399-pwmrockchip,rk3288-pwmÈÿB±˜default¦yík õdisabledpwm@ff420010(rockchip,rk3399-pwmrockchip,rk3288-pwmÈÿB±˜default¦zík õdisabledpwm@ff420020(rockchip,rk3399-pwmrockchip,rk3288-pwmÈÿB ±˜default¦{ík õdisabledpwm@ff420030(rockchip,rk3399-pwmrockchip,rk3288-pwmÈÿB0±˜default¦|ík õdisableddfi@ff630000Èÿc@rockchip,rk3399-dfiÍüƒíy épclk_ddr_mon õdisabledLvideo-codec@ff650000rockchip,rk3399-vpuÈÿe ürq vepuvdpuíëê éaclkhclk¼}iommu@ff650800rockchip,iommuÈÿe@üsíëê éaclkifaceÃL}video-codec@ff660000rockchip,rk3399-vdecÈÿf€üt íí쟞éaxiahbcabaccore¼~ iommu@ff660480rockchip,iommu Èÿf€@ÿfÀ@üuííì éaclkiface ÃL~iommu@ff670800rockchip,iommuÈÿg@ü*íáÝ éaclkifaceà õdisabledrga@ff680000rockchip,rk3399-rgaÈÿhü7íÜåméaclkhclksclkÝjgi äcoreaxiahb!efuse@ff690000rockchip,rk3399-efuseÈÿi€+í} épclk_efusecpu-id@7Ècpu-leakage@17Ègpu-leakage@18Ècenter-leakage@19Ècpu-leakage@1aÈlogic-leakage@1bÈwafer-info@1cÈdma-controller@ff6d0000arm,pl330arm,primecellÈÿm@ üÐÛíÓ éapb_pclkLIdma-controller@ff6e0000arm,pl330arm,primecellÈÿn@ üÐÛíÔ éapb_pclkL8clock-controller@ff750000rockchip,rk3399-pmucruÈÿuíéxin24mAòDkT(JñLkclock-controller@ff760000rockchip,rk3399-cruÈÿvíéxin24mAòˆDÀÀ@ÂÁBÉÂCãÞxíDT#g¸€/¯;šÊðÑ€xhÀ<4`õáõáúð€#ÃFõáúð€ׄׄ ë ëÂׄLsyscon@ff770000&rockchip,rk3399-grfsysconsimple-mfdÈÿw+Lio-domains"rockchip,rk3399-io-voltage-domainõokayÿ€ � &‚mipi-dphy-rx0rockchip,rk3399-mipi-dphy-rx0íw¥oédphy-refdphy-cfggrf6 õdisabledL•usb2phy@e450rockchip,rk3399-usb2phyÈäPí{éphyclkA.clk_usbphy0_480m õdisabledL"host-port6ü linestate õdisabledL#otg-port60üghjotg-bvalidotg-idlinestate õdisabledL&usb2phy@e460rockchip,rk3399-usb2phyÈä`í|éphyclkA.clk_usbphy1_480m õdisabledL$host-port6ü linestate õdisabledL%otg-port60ülmootg-bvalidotg-idlinestate õdisabledL(phy@f780rockchip,rk3399-emmc-phyÈ÷€$íƒéemmcclkA26õokayL!pcie-phyrockchip,rk3399-pcie-phyíŠérefclk6݇äphy õdisabledLphy@ff7c0000rockchip,rk3399-typec-phyÈÿ|í~}étcpdcoretcpdphy-refD~Túð€Ý•”Läuphyuphy-pipeuphy-tcphy õdisableddp-port6L*usb3-port6L'phy@ff800000rockchip,rk3399-typec-phyÈÿ€í€étcpdcoretcpdphy-refD€Túð€ Ý�œMäuphyuphy-pipeuphy-tcphy õdisableddp-port6L+usb3-port6L)watchdog@ff848000 rockchip,rk3399-wdtsnps,dw-wdtÈÿ„€í|üxrktimer@ff850000rockchip,rk3399-timerÈÿ…üQíhZ épclktimerspdif@ff870000rockchip,rk3399-spdifÈÿ‡üB I%tx émclkhclkíUטdefault¦„³ õdisabledi2s@ff880000(rockchip,rk3399-i2srockchip,rk3066-i2sÈÿˆü' II%txrxéi2s_clki2s_hclkíVÔ˜bclk_onbclk_off¦…¥†³ õdisabledi2s@ff890000(rockchip,rk3399-i2srockchip,rk3066-i2sÈÿ‰ü( II%txrxéi2s_clki2s_hclkíWÕ˜default¦‡³ õdisabledi2s@ff8a0000(rockchip,rk3399-i2srockchip,rk3066-i2sÈÿŠü) II%txrxéi2s_clki2s_hclkíXÖ³ õdisabledL˜vop@ff8f0000rockchip,rk3399-vop-lit Èÿ� ÿ� üwDÛÛTׄõáíÛµÛéaclk_vopdclk_vophclk_vop¼ˆÝ äaxiahbdclk õdisabledport+Lendpoint@0ÈĉL�endpoint@1ÈÄŠL¢endpoint@2ÈÄ‹L›endpoint@3ÈÄŒLŸendpoint@4ÈÄ�L-iommu@ff8f3f00rockchip,iommuÈÿ�?üwíÛÛ éaclkifaceà õdisabledLˆvop@ff900000rockchip,rk3399-vop-big Èÿ� ÿ� üvDÙÙTׄõáíÙ´Ùéaclk_vopdclk_vophclk_vop¼ŽÝ äaxiahbdclk õdisabledport+Lendpoint@0ÈÄ�L¡endpoint@1ÈÄ�Lœendpoint@2ÈÄ‘Lšendpoint@3ÈÄ’Lžendpoint@4ÈÄ“L,iommu@ff903f00rockchip,iommuÈÿ�?üvíÙÙ éaclkifaceà õdisabledLŽisp0@ff910000rockchip,rk3399-cif-ispÈÿ‘@ü+ínéãéispaclkhclk¼”Ç•Ìdphy õdisabledports+port@0È+iommu@ff914000rockchip,iommu Èÿ‘@ÿ‘Pü+íéã éaclkifaceÃUL”isp1@ff920000rockchip,rk3399-cif-ispÈÿ’@ü,íoêäéispaclkhclk¼–Ç—Ìdphy õdisabledports+port@0È+iommu@ff924000rockchip,iommu Èÿ’@ÿ’Pü,íêä éaclkifaceÃUL–hdmi-soundsimple-audio-cardpi2s‰ £hdmi-sound õdisabledsimple-audio-card,cpuº˜simple-audio-card,codecº™hdmi@ff940000rockchip,rk3399-dw-hdmiÈÿ”ü(ítqpoéiahbisfrcecgrfref³ õdisabledL™ports+port@0È+endpoint@0ÈÄšL‘endpoint@1ÈÄ›L‹port@1Èmipi@ff960000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsiÈÿ–€ü- í¢p£oérefpclkphy_cfggrfÝûäapb+ õdisabledports+port@0È+endpoint@0ÈÄœL�endpoint@1ÈÄ�L‰mipi@ff968000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsiÈÿ–€€ü. í¢q¤oérefpclkphy_cfggrfÝüäapb+6 õdisabledL—ports+port@0È+endpoint@0ÈÄžL’endpoint@1ÈÄŸLŒedp@ff970000rockchip,rk3399-edpÈÿ—€ü íjlo édppclkgrf˜default¦ Ýädp õdisabledports+port@0È+endpoint@0ÈÄ¡L�endpoint@1ÈÄ¢LŠgpu@ff9a0000#rockchip,rk3399-maliarm,mali-t860Èÿš0ü jobmmugpuíÐô# õdisabled-£LRpinctrlrockchip,rk3399-pinctrlÍ+Ögpio@ff720000rockchip,gpio-bankÈÿríküÄÔðXLgpio@ff730000rockchip,gpio-bankÈÿsíküÄÔðXLrgpio@ff780000rockchip,gpio-bankÈÿxíPüÄÔðXgpio@ff788000rockchip,gpio-bankÈÿx€íQüÄÔðXLªgpio@ff790000rockchip,gpio-bankÈÿyíRüÄÔðXpcfg-pull-upàL§pcfg-pull-downíL¨pcfg-pull-noneüL¤pcfg-pull-none-12maü L¦pcfg-pull-none-13maü L¥pcfg-pull-none-18maü pcfg-pull-none-20maü pcfg-pull-up-2maà pcfg-pull-up-8maà pcfg-pull-up-18maà pcfg-pull-up-20maà pcfg-pull-down-4maí pcfg-pull-down-8maí pcfg-pull-down-12maí pcfg-pull-down-18maí pcfg-pull-down-20maí pcfg-output-high pcfg-output-low $pcfg-input-enable /pcfg-input-pull-up /àpcfg-input-pull-down /íclockclk-32k <¤cifcif-clkin < ¤cif-clkouta < ¤edpedp-hpd <¤L gmacrgmii-pinsð <¥¤ ¤ ¥ ¤ ¤¤¤¤¥¥¤¤¥¥rmii-pins  < ¤ ¥ ¤ ¤ ¤¤¤¤¥¥i2c0i2c0-xfer <¤¤Lqi2c1i2c1-xfer <¤¤L.i2c2i2c2-xfer <¦¦L/i2c3i2c3-xfer <¤¤L0i2c4i2c4-xfer < ¤ ¤Lwi2c5i2c5-xfer < ¤ ¤L1i2c6i2c6-xfer < ¤ ¤L2i2c7i2c7-xfer <¤¤L3i2c8i2c8-xfer <¤¤Lxi2s0i2s0-2ch-bus` <¤¤¤¤¤¤i2s0-2ch-bus-bclk-off` <¤¤¤¤¤¤i2s0-8ch-bus� <¤¤¤¤¤¤¤¤¤L…i2s0-8ch-bus-bclk-off� <¤¤¤¤¤¤¤¤¤L†i2s1i2s1-2ch-busP <¤¤¤¤¤L‡i2s1-2ch-bus-bclk-offP <¤¤¤¤¤sdio0sdio0-bus1 <§sdio0-bus4@ <§§§§sdio0-cmd <§sdio0-clk <¤sdio0-cd <§sdio0-pwr <§sdio0-bkpwr <§sdio0-wp <§sdio0-int <§sdmmcsdmmc-bus1 <§sdmmc-bus4@ <§ § § §Lsdmmc-clk < ¤Lsdmmc-cmd < §Lsdmmc-cd <§Lsdmmc-wp <§suspendap-pwroff <¤ddrio-pwroff <¤spdifspdif-bus <¤L„spdif-bus-1 <¤spi0spi0-clk <§L9spi0-cs0 <§L<spi0-cs1 <§spi0-tx <§L:spi0-rx <§L;spi1spi1-clk < §L=spi1-cs0 < §L@spi1-rx <§L?spi1-tx <§L>spi2spi2-clk < §LAspi2-cs0 < §LDspi2-rx < §LCspi2-tx < §LBspi3spi3-clk <§Llspi3-cs0 <§Lospi3-rx <§Lnspi3-tx <§Lmspi4spi4-clk <§LEspi4-cs0 <§LHspi4-rx <§LGspi4-tx <§LFspi5spi5-clk <§LJspi5-cs0 <§LMspi5-rx <§LLspi5-tx <§LKtestclktest-clkout0 <¤test-clkout1 <¤test-clkout2 <¤tsadcotp-pin <¤LSotp-out <¤LTuart0uart0-xfer <§¤L4uart0-cts <¤uart0-rts <¤uart1uart1-xfer < § ¤L5uart2auart2a-xfer <§ ¤uart2buart2b-xfer <§¤uart2cuart2c-xfer <§¤L6uart3uart3-xfer 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Ÿt{vcc-sys-regulatorregulator-fixedévcc_sysø Ltvcc3v3-sys-regulatorregulator-fixed évcc3v3_sysø 2Z 62Z  ªtLvcc1v8-s3-regulatorregulator-fixed évcca1v8_s3w@6w@ ªø vcc1v8-codec-regulatorregulator-fixed µ Ȫ˜default¦« évcc1v8_codecw@6w@ ª compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4mmc0mmc1mmc2cpudevice_typeregenable-methodcapacity-dmips-mhzclocks#cooling-cellsdynamic-power-coefficientcpu-idle-statesoperating-points-v2cpu-supplyphandleduration-usexit-latency-usentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usmin-residency-usportsrockchip,pmudevfreq-eventsclock-namesstatusinterruptsarm,no-tick-in-suspendclock-frequencyclock-output-names#clock-cellsreg-names#interrupt-cellsaspm-no-l0sbus-rangeinterrupt-namesinterrupt-map-maskinterrupt-mapmax-link-speedmsi-mapphysphy-namesrangesresetsreset-namesinterrupt-controllerpower-domainsrockchip,grfsnps,txpblmax-frequencyfifo-depthassigned-clocksassigned-clock-ratesbus-widthcap-sd-highspeedcd-gpiosdisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplyarasan,soc-ctl-syscondisable-cqe-dcmdmmc-hs200-1_8vnon-removabledr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirk#sound-dai-cellsremote-endpointmsi-controller#msi-cellsaffinity#io-channel-cellsreg-shiftreg-io-widthdmasdma-namespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#power-domain-cellspm_qospmu1830-supplyi2c-scl-rising-time-nsi2c-scl-falling-time-nsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendfcs,suspend-voltage-selector#pwm-cellsiommus#iommu-cells#dma-cellsarm,pl330-periph-burst#reset-cellsbt656-supplyaudio-supplysdmmc-supplygpio1830-supply#phy-cellsdrive-impedance-ohmrockchip,disable-mmu-resetsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namesound-daigpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsstdout-pathdebounce-intervallabellinux,codevin-supplyenable-active-highgpio