Ð þíÕ8Éd( ŸÉ, 6,pine64,soquartz-bladepine64,soquartzrockchip,rk3566.7PINE64 RK3566 SOQuartz on Blade carrier boardaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe010000ç/mmc@fe2b0000ì/mmc@fe310000ñ/mmc@fe2c0000cpus cpu@0öcpu,arm,cortex-a55 psci*>I cpu@100öcpu,arm,cortex-a55 psci*>I cpu@200öcpu,arm,cortex-a55 psci*>I cpu@300öcpu,arm,cortex-a55 psci*>I opp-table-0,operating-points-v2QIopp-408000000\Q– c »  » Œ0qœ@opp-600000000\#ÃF c »  » Œ0opp-816000000\0£, c »  » Œ0‚opp-1104000000\AÍ´ c »  » Œ0opp-1416000000\Tfr c »  » Œ0opp-1608000000\_Ø" cà˜à˜Œ0opp-1800000000\kIÒ c��Œ0display-subsystem,rockchip,display-subsystemŽfirmwarescmi ,arm,scmi-smc”‚Ÿ protocol@14¥Iopp-table-1,operating-points-v2I@opp-200000000\ ëÂc –¨opp-300000000\á£c –¨opp-400000000\ׄc –¨opp-600000000\#ÃFc –¨opp-700000000\)¹'c » opp-800000000\/¯cB@hdmi-sound,simple-audio-card²HDMIÉi2sâüokaysimple-audio-card,codecsimple-audio-card,cpupmu,arm,cortex-a55-pmu0 äåæç psci ,arm,psci-1.0#smctimer,arm,armv8-timer0    +xin24m ,fixed-clockBn6Rxin24m¥Ixin32k ,fixed-clockB€Rxin32ke odefault¥sram@10f000 ,mmio-sramð }ðsram@0,arm,scmi-shmemIsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü@›œ�„satapmaliverxoob  _� •sata-phyŸ± üdisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü€ ¡¢„satapmaliverxoob  `� •sata-phyŸ± üdisabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3üÀ@  ©¦§¥„ref_clksuspend_clkbus_clk¿otg Çutmi_wide±Ð”×üokay� •usb2-phyð ÷high-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ý@  ª©ª¨„ref_clksuspend_clkbus_clk¿host �•usb2-phyusb3-phy Çutmi_wide±Ð•× üdisabledinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF   +ýA5(@Iusb@fd800000 ,generic-ehciý€  ‚½¾¼�•usb üdisabledusb@fd840000 ,generic-ohciý„  ƒ½¾¼�•usb üdisabledusb@fd880000 ,generic-ehciýˆ  …¿À¼�•usb üdisabledusb@fd8c0000 ,generic-ohciýŒ  †¿À¼�•usb üdisabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdýÂI»io-domains&,rockchip,rk3568-pmu-io-voltage-domainüokayO]ky‡•£±¿syscon@fdc50000ýÅ ,rockchip,rk3566-pipe-grfsysconIµsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýÆIsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýÈI¶syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýÉI·syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€I¸syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€Iºclock-controller@fdd00000,rockchip,rk3568-pmucruýÐ¥ÍIclock-controller@fdd20000,rockchip,rk3568-cruýÒ„xin24m¥ÍÚêG†Œ ëÂÿIi2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ  .- „i2cpclkeodefault üokayregulator@1c ,tcs,tcs4525 )vdd_cpu8 5PŒ0hü}‘£Iregulator-state-mem®pmic@20,rockchip,rk809   ¥Rrk808-clkout1rk808-clkout2odefaulte!Çèö""""&"2">"J"V"I”regulatorsDCDC_REG1 )vdd_logic}‘8¡ P™pb » hq{regulator-state-mem’ª » DCDC_REG2)vdd_gpu}‘8¡ P™pb » hq{IAregulator-state-mem®DCDC_REG3}‘{)vcc_ddrregulator-state-mem’DCDC_REG4}‘8¡ P™pb » {)vdd_npuregulator-state-mem®DCDC_REG5)vcc_1v8}‘8w@Pw@Iregulator-state-mem’ªw@LDO_REG1}‘8 » P » )vdda0v9_imageIVregulator-state-mem’ª » LDO_REG2}‘8 » P »  )vdda_0v9regulator-state-mem®LDO_REG3}‘8 » P »  )vdda0v9_pmuregulator-state-mem’ª » LDO_REG4}‘82Z P2Z  )vccio_acodecregulator-state-mem®LDO_REG5}‘8w@P2Z  )vccio_sdIregulator-state-mem®LDO_REG6}‘82Z P2Z  )vcc3v3_pmuIregulator-state-mem’ª2Z LDO_REG7}‘8w@Pw@ )vcca_1v8I¨regulator-state-mem®LDO_REG8}‘8w@Pw@ )vcca1v8_pmuI™regulator-state-mem®LDO_REG9}‘8w@Pw@)vcca1v8_imageIWregulator-state-mem®SWITCH_REG1)vcc_3v3Iregulator-state-mem®SWITCH_REG2 )vcc3v3_sd üdisabledregulator-state-mem’serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ  t ,„baudclkapb_pclkÆ##e$odefaultËØ üdisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý× 0 „pwmpclke%odefaultâ üdisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý× 0 „pwmpclke&odefaultâ üdisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 „pwmpclke'odefaultâ üdisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0 0 „pwmpclke(odefaultâ üdisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controllerí Ipower-domain@7)ípower-domain@8ÌÍ *+,ípower-domain@9 ÚÛÜ -./ípower-domain@10 ñò012345ípower-domain@11 í6ípower-domain@13 7ípower-domain@14 89:ípower-domain@15;<=>?ígpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$ ()' jobmmugpu„gpubus *@±üokayAI¥video-codec@fdea0400,rockchip,rk3568-vpuýê  ‹vdpuîï „aclkhclk$B± iommu@fdea0800,rockchip,rk3568-iommuýê@  Š „aclkifaceîï± +IBvideo-codec@fdee0000,rockchip,rk3568-vepuýî  @ýþ „aclkhclk$C± iommu@fdee0800,rockchip,rk3568-iommuýî@  ?ýþ „aclkiface± +ICmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@  d ÁÂŽ�„biuciuciu-driveciu-sample8CðÑ€ÐëQreset üdisabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ macirqeth_wake_irq@†‰‰ÇÃĉÈW„stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refÐì Qstmmacethÿ]Dm~E‘F¤üokayÚ‰‡†­‡†GÄinputÑÜrgmiiodefaulteHIJKLM å õ  N †  0)2Nmdio,snps,dwmac-mdio ethernet-phy@0,ethernet-phy-ieee802.3-c22üokayINstmmac-axi-config=GWIDrx-queues-configgIEqueue0tx-queues-config}IFqueue0vop@fe040000 þ0þ@“vopgamma-lut  ”(ÝÞßàá%„aclkhclkdclk_vp0dclk_vp1dclk_vp2$O± ÿüokay,rockchip,rk3566-vopÚßà­ports Iport@0 endpoint@2�PIXport@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ?  ”ÝÞ „aclkiface+± üokayIOdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ  D „pclkhclkèÚ•dphy�Q± QapbÐÿ üdisabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ  E „pclkhclkéÚ•dphy�R± QapbÐÿ üdisabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ   -(æç“(Ú„iahbisfrcecrefodefault eSTU± Ëÿ­üokay¾VÎWIports port@0endpoint�XIPport@1endpoint�YIÅqos@fe128000,rockchip,rk3568-qossysconþ€ I)qos@fe138080,rockchip,rk3568-qossysconþ€€ I8qos@fe138100,rockchip,rk3568-qossysconþ� I9qos@fe138180,rockchip,rk3568-qossysconþ�€ I:qos@fe148000,rockchip,rk3568-qossysconþ€ I*qos@fe148080,rockchip,rk3568-qossysconþ€€ I+qos@fe148100,rockchip,rk3568-qossysconþ� I,qos@fe150000,rockchip,rk3568-qossysconþ I6qos@fe158000,rockchip,rk3568-qossysconþ€ I0qos@fe158100,rockchip,rk3568-qossysconþ� I1qos@fe158180,rockchip,rk3568-qossysconþ�€ I2qos@fe158200,rockchip,rk3568-qossysconþ‚ I3qos@fe158280,rockchip,rk3568-qossysconþ‚€ I4qos@fe158300,rockchip,rk3568-qossysconþƒ I5qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ I;qos@fe190280,rockchip,rk3568-qossysconþ€ I<qos@fe190300,rockchip,rk3568-qossysconþ I=qos@fe190380,rockchip,rk3568-qossysconþ€ I>qos@fe190400,rockchip,rk3568-qossysconþ I?qos@fe198000,rockchip,rk3568-qossysconþ€ I7qos@fe1a8000,rockchip,rk3568-qossysconþ€ I-qos@fe1a8080,rockchip,rk3568-qossysconþ€€ I.qos@fe1a8100,rockchip,rk3568-qossysconþ� I/pcie@fe260000,rockchip,rk3568-pcie0À@þ&ô“dbiapbconfig< KJIHGsyspmcmsglegacyerrÞ(�‚ƒ„…$„aclk_mstaclk_slvaclk_dbipclkauxöpciè`ûZZZZ )8GO� •pcie-phy±T}ôôô ô à@СQpipe üokayodefaulte[ Y\ e]legacy-interrupt-controller  HIZmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@  b °±Š‹„biuciuciu-driveciu-sample8CðÑ€ÐÔQresetüokayu‰šodefaulte^_`a¥²bmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@  c ²³Œ�„biuciuciu-driveciu-sample8CðÑ€ÐÖQresetüokay‰¾Ëácìodefault edefú²"¥spi@fe300000 ,rockchip,sfcþ0@  exv„clk_sfchclk_sfcegodefault üdisabledmmc@fe310000,rockchip,rk3568-dwcmshcþ1  Ú{}ê ëÂn6(|zy{}„corebusaxiblocktimerüokay ì²¥i2s@fe400000,rockchip,rk3568-i2s-tdmþ@  4Ú=AêFÏqFÏq?C9„mclk_txmclk_rxhclkÆh txÐPQ Qtx-mrx-mÿ­üokayIi2s@fe410000,rockchip,rk3568-i2s-tdmþA  5ÚEIêFÏqFÏqGK:„mclk_txmclk_rxhclkÆhh rxtxÐRS Qtx-mrx-mÿodefault0eijklmnopqrst­ üdisabledi2s@fe420000,rockchip,rk3568-i2s-tdmþB  6ÚMêFÏqOO;„mclk_txmclk_rxhclkÆhh txrxÐTQmÿodefaulteuvwx­ üdisabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC  7SW<„mclk_txmclk_rxhclkÆhh txrxÐUV Qtx-mrx-mÿ­ üdisabledpdm@fe440000,rockchip,rk3568-pdmþD  LZY„pdm_clkpdm_hclkÆh  rxeyz{|}~odefaultÐXQpdm-m­ üdisabledspdif@fe460000,rockchip,rk3568-spdifþF  f „mclkhclk_\Æh txodefaulte­ üdisableddma-controller@fe530000,arm,pl330arm,primecellþS@     „apb_pclk 7I#dma-controller@fe550000,arm,pl330arm,primecellþU@    „apb_pclk 7Ihi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ  /HG „i2cpclke€odefault üokayi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[  0JI „i2cpclke�odefault  üdisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\  1LK „i2cpclke‚odefault  üdisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ]  2NM „i2cpclkeƒodefault  üdisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^  3PO „i2cpclke„odefault  üdisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ`  • „tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa  gRQ„spiclkapb_pclkÆ## txrxodefault e…†‡  üdisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb  hTS„spiclkapb_pclkÆ## txrxodefault eˆ‰Š  üdisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc  iVU„spiclkapb_pclkÆ## txrxodefault e‹Œ�  üdisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd  jXW„spiclkapb_pclkÆ## txrxodefault eŽ��  üdisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe  u„baudclkapb_pclkÆ## e‘’“odefaultËØüokay Bbluetooth,brcm,bcm43438-bt”„lpo R• f• x•odefault e–—˜ ‡" “™serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf  v# „baudclkapb_pclkÆ##ešodefaultËØüokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg  w'$„baudclkapb_pclkÆ##e›odefaultËØ üdisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh  x+(„baudclkapb_pclkÆ## eœodefaultËØ üdisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi  y/,„baudclkapb_pclkÆ# # e�odefaultËØ üdisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj  z30„baudclkapb_pclkÆ# # ežodefaultËØ üdisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk  {74„baudclkapb_pclkÆ##eŸodefaultËØüokayserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl  |;8„baudclkapb_pclkÆ##e odefaultËØ üdisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm  }?<„baudclkapb_pclkÆ##e¡odefaultËØ üdisabledthermal-zonescpu-thermal  d ¶è Ä¢tripscpu_alert0 Ôp àÐýpassiveI£cpu_alert1 Ô$ø àÐýpassivecpu_crit Ôs àÐ ýcriticalcooling-mapsmap0 ë£0 ð ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal   ¶è Ä¢tripsgpu-threshold Ôp àÐýpassivegpu-target Ô$ø àÐýpassiveI¤gpu-crit Ôs àÐ ýcriticalcooling-mapsmap0 ë¤ ð¥ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq  sÚêf@ ®`„tsadcapb_pclkÐ�‚×ÿ ÿsoinitdefaultsleepe¦ § ¦ *üokayI¢saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr  ]„saradcapb_pclkЀ Qsaradc-apb @ üdisabled R¨pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY „pwmpclke©odefaultâ üdisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY „pwmpclkeªodefaultâ üdisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY „pwmpclke«odefaultâ üdisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0ZY „pwmpclke¬odefaultâ üdisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ „pwmpclke­odefaultâ üdisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ „pwmpclke®odefaultâ üdisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ „pwmpclke¯odefaultâ üdisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0]\ „pwmpclke°odefaultâ üdisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ „pwmpclke±odefaultâ üdisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ „pwmpclke²odefaultâ üdisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ „pwmpclke³odefaultâ üdisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0`_ „pwmpclke´odefaultâ üdisabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ"} „refapbpipeÚ"êõáÐÇ ^µ p¶ † üdisabledIphy@fe840000,rockchip,rk3568-naneng-combphyþ„%~ „refapbpipeÚ%êõáÐÉ ^µ p· †üokayÑ"Iphy@fe870000,rockchip,rk3568-csi-dphyþ‡y„pclk †ÐºQapbÿ üdisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ… „refpclkz †± Qapbл üdisabledIQmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ† „refpclk{ †± Qapbм üdisabledIRusb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠ„phyclkRclk_usbphy0_480m  ‡ ‘¸¥üokayIhost-port † üdisabledIotg-port †üokayѹIusb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹„phyclkRclk_usbphy1_480m  ˆ ‘º¥ üdisabledhost-port † üdisabledIotg-port † üdisabledIpinctrl,rockchip,rk3568-pinctrlÿ ¡» }gpio@fdd60000,rockchip,gpio-bankýÖ  !.  ® ¾I nextrst-hog Ê_ ÓnEXTRST Ýgpio@fe740000,rockchip,gpio-bankþt  "cd ® ¾I\gpio@fe750000,rockchip,gpio-bankþu  #ef ® ¾I•gpio@fe760000,rockchip,gpio-bankþv  $gh ® ¾gpio@fe770000,rockchip,gpio-bankþw  %ij ® ¾pcfg-pull-up èI¾pcfg-pull-down õIÄpcfg-pull-none I¼pcfg-pull-none-drv-level-1  IÀpcfg-pull-none-drv-level-2  I¿pcfg-pull-none-drv-level-3  IÃpcfg-pull-up-drv-level-1 è IÂpcfg-pull-up-drv-level-2 è I½pcfg-pull-none-smt  IÁacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 5¼I cpuebcedpdpemmceth0eth1flashfspifspi-pins` 5¼¼¼¼¼¼Iggmac0gmac1gmac1m0-miim 5¼¼IHgmac1m0-clkinout 5¼ILgmac1m0-rx-bus20 5 ¼ ¼ ¼IJgmac1m0-tx-bus20 5 ¿¿¼IIgmac1m0-rgmii-clk 5¼ÀIKgmac1m0-rgmii-bus@ 5¼¼¿¿IMgpuhdmitxhdmitxm0-cec 5¼IUhdmitx-scl 5¼IShdmitx-sda 5¼ITi2c0i2c0-xfer 5 Á ÁIi2c1i2c1-xfer 5 Á ÁI€i2c2i2c2m1-xfer 5 Á ÁI�i2c3i2c3m0-xfer 5ÁÁI‚i2c4i2c4m1-xfer 5 Á ÁIƒi2c5i2c5m0-xfer 5 Á ÁI„i2s1i2s1m1-lrckrx 5¼Ili2s1m1-lrcktx 5¼Iki2s1m1-sclkrx 5¼Iji2s1m1-sclktx 5¼Iii2s1m1-sdi0 5¼Imi2s1m1-sdi1 5¼Ini2s1m1-sdi2 5¼Ioi2s1m1-sdi3 5¼Ipi2s1m1-sdo0 5¼Iqi2s1m1-sdo1 5¼Iri2s1m1-sdo2 5 ¼Isi2s1m1-sdo3 5 ¼Iti2s2i2s2m0-lrcktx 5¼Ivi2s2m0-sclktx 5¼Iui2s2m0-sdi 5¼Iwi2s2m0-sdo 5¼Ixi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk 5¼Iypdmm0-clk1 5¼Izpdmm0-sdi0 5 ¼I{pdmm0-sdi1 5 ¼I|pdmm0-sdi2 5 ¼I}pdmm0-sdi3 5¼I~pmicpmic-int-l 5¾I!pmupwm0pwm0m0-pins 5¼I%pwm1pwm1m0-pins 5¼I&pwm2pwm2m0-pins 5¼I'pwm3pwm3-pins 5¼I(pwm4pwm4-pins 5¼I©pwm5pwm5-pins 5¼Iªpwm6pwm6-pins 5¼I«pwm7pwm7-pins 5¼I¬pwm8pwm8m0-pins 5 ¼I­pwm9pwm9m0-pins 5 ¼I®pwm10pwm10m0-pins 5 ¼I¯pwm11pwm11m0-pins 5¼I°pwm12pwm12m0-pins 5¼I±pwm13pwm13m0-pins 5¼I²pwm14pwm14m0-pins 5¼I³pwm15pwm15m0-pins 5¼I´refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ 5½½½½I^sdmmc0-clk 5½I_sdmmc0-cmd 5½I`sdmmc0-det 5¾Iasdmmc1sdmmc1-bus4@ 5½½½½Idsdmmc1-clk 5½Ifsdmmc1-cmd 5½Iesdmmc2spdifspdifm0-tx 5¼Ispi0spi0m0-pins0 5 ¼¼¼I‡spi0m0-cs0 5¼I…spi0m0-cs1 5¼I†spi1spi1m0-pins0 5 ¼¼¼IŠspi1m0-cs0 5¼Iˆspi1m0-cs1 5¼I‰spi2spi2m0-pins0 5¼¼¼I�spi2m0-cs0 5¼I‹spi2m0-cs1 5¼IŒspi3spi3m0-pins0 5 ¼¼ ¼I�spi3m0-cs0 5¼IŽspi3m0-cs1 5¼I�tsadctsadc-shutorg 5¼I§tsadc-pin 5¼I¦uart0uart0-xfer 5¾¾I$uart1uart1m0-xfer 5 ¾ ¾I‘uart1m0-ctsn 5¼I’uart1m0-rtsn 5 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)vcc3v0_sd}‘82Z P2Z £"Ibvcc3v3-pcie-regulator,regulator-fixed)vcc3v3_pcie_p}‘82Z P2Z £¹I]vcc5v-dcin-regulator,regulator-fixed )vcc5v_dcin}‘8LK@PLK@IÉ interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supplyregulator-off-in-suspendrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-init-microvoltregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsfifo-depthmax-frequencyreset-namessnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlesnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplybus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplybroken-cdbus-widthcap-sd-highspeeddisable-wpvqmmc-supplyvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr50mmc-hs200-1_8vdma-namesarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosvbat-supplyvddio-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfrockchip,pmugpio-controller#gpio-cellsgpio-hogline-nameoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathlabeldefault-statelinux,default-triggerretain-state-suspendedcolorfunction