Ð þíéÕ8Þä( ñÞ¬ *,rockchip,rk3568-bpi-r2prorockchip,rk3568$7Bananapi-R2 Pro (RK3568) DDR4 Boardaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe2a0000ç/ethernet@fe010000ñ/mmc@fe2b0000ö/mmc@fe310000cpus cpu@0ûcpu,arm,cortex-a55 !psci/Ccpu@100ûcpu,arm,cortex-a55!psci/C cpu@200ûcpu,arm,cortex-a55!psci/C cpu@300ûcpu,arm,cortex-a55!psci/C opp-table-0,operating-points-v2KCopp-408000000VQ– ] »  » Œ0kœ@opp-600000000V#ÃF ] »  » Œ0opp-816000000V0£, ] »  » Œ0|opp-1104000000VAÍ´ ] »  » Œ0opp-1416000000VTfr ] »  » Œ0opp-1608000000V_Ø" ]à˜à˜Œ0opp-1800000000VkIÒ ]��Œ0opp-1992000000Vv»‚ ]Œ0Œ0Œ0display-subsystem,rockchip,display-subsystemˆfirmwarescmi ,arm,scmi-smcŽ‚™ protocol@14ŸCopp-table-1,operating-points-v2CBopp-200000000V ëÂ] –¨opp-300000000Vá£] –¨opp-400000000Vׄ] –¨opp-600000000V#ÃF] –¨opp-700000000V)¹'] » opp-800000000V/¯]B@hdmi-sound,simple-audio-card¬HDMIÃi2sÜöokaysimple-audio-card,codecýsimple-audio-card,cpuýpmu,arm,cortex-a55-pmu0äåæç psci ,arm,psci-1.0(smctimer,arm,armv8-timer0   %xin24m ,fixed-clock<n6Lxin24mŸCxin32k ,fixed-clock<€Lxin32k_ idefaultŸsram@10f000 ,mmio-sramð wðsram@0,arm,scmi-shmemCsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü@ › œ �~satapmaliverxoob _Š �sata-phy™« ödisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü€   ¡ ¢~satapmaliverxoob `Š �sata-phy™«öokayusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3üÀ@ © ¦ § ¥~ref_clksuspend_clkbus_clk¹host Áutmi_wide«Ê ”Ñöokay Š�usb2-phyusb3-phyusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ý@ ª © ª ¨~ref_clksuspend_clkbus_clk¹host Š�usb2-phyusb3-phy Áutmi_wide«Ê •Ñöokayinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF  êÿýA(%Cusb@fd800000 ,generic-ehciý€ ‚ ½ ¾ ¼Š�usböokayusb@fd840000 ,generic-ohciý„ ƒ ½ ¾ ¼Š�usböokayusb@fd880000 ,generic-ehciýˆ … ¿ À ¼Š�usböokayusb@fd8c0000 ,generic-ohciýŒ † ¿ À ¼Š�usböokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdýÂC±io-domains&,rockchip,rk3568-pmu-io-voltage-domainöokay4BP^lzˆ–syscon@fdc50000ýÅ ,rockchip,rk3568-pipe-grfsysconCªsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýÆCsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýÈC«syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýÉC¬syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€C­syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€C°clock-controller@fdd00000,rockchip,rk3568-pmucruýП¤Cclock-controller@fdd20000,rockchip,rk3568-cruýÒ ~xin24mŸ¤± ÁG†Œ ëÂÖC i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ . - ~i2cpclk_idefault öokaypmic@20,rockchip,rk809 Ÿidefault_ ã!!!(!4!@!L!X!d!pregulatorsDCDC_REG1 ~vdd_logic�¡³ » Ìã¡ û™pqregulator-state-mem(DCDC_REG2~vdd_gpu�³ » Ìã¡ û™pqCCregulator-state-mem(DCDC_REG3~vcc_ddr�¡Ìregulator-state-memADCDC_REG4~vdd_npu³ » Ìã¡ û™pqregulator-state-mem(DCDC_REG5~vcc_1v8�¡ãw@ûw@Cregulator-state-mem(LDO_REG1~vdda0v9_image�ã » û » CWregulator-state-mem(LDO_REG2 ~vdda_0v9�¡ã » û » regulator-state-mem(LDO_REG3 ~vdda0v9_pmu�¡ã » û » regulator-state-memAY » LDO_REG4 ~vccio_acodec�¡ã2Z û2Z Cregulator-state-mem(LDO_REG5 ~vccio_sd�¡ãw@û2Z Cregulator-state-mem(LDO_REG6 ~vcc3v3_pmu�¡ã2Z û2Z Cregulator-state-memAY2Z LDO_REG7 ~vcca_1v8�¡ãw@ûw@C�regulator-state-mem(LDO_REG8 ~vcca1v8_pmu�¡ãw@ûw@regulator-state-memAYw@LDO_REG9~vcca1v8_image�ãw@ûw@CXregulator-state-mem(SWITCH_REG1~vcc_3v3�¡Cregulator-state-mem(SWITCH_REG2 ~vcc3v3_sd�C`regulator-state-mem(serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ t  ,~baudclkapb_pclku""_#idefaultz‡ ödisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 ~pwmpclk_$idefault‘ ödisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 ~pwmpclk_%idefault‘ ödisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×   0 ~pwmpclk_&idefault‘ ödisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0  0 ~pwmpclk_'idefault‘ ödisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controllerœ Cpower-domain@7  °(œpower-domain@8 Ì Í °)*+œpower-domain@9  Ú Û Ü °,-.œpower-domain@10  ñ ò°/01234œpower-domain@11  í°5œpower-domain@13  °6œpower-domain@14  °789œpower-domain@15  °:;<=>?@Aœgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$()' ·jobmmugpu  ~gpubus/B«öokayÇCCšvideo-codec@fdea0400,rockchip,rk3568-vpuýê ‹·vdpu î ï ~aclkhclkÓD« iommu@fdea0800,rockchip,rk3568-iommuýê@ Š ~aclkiface î ï« ÚCDvideo-codec@fdee0000,rockchip,rk3568-vepuýî @ ý þ ~aclkhclkÓE« iommu@fdee0800,rockchip,rk3568-iommuýî@ ? ý þ ~aclkiface« ÚCEmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ d  Á  Ž �~biuciuciu-driveciu-sampleçòðÑ€Ê ëreset ödisabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ ·macirqeth_wake_irq@ † ‰ ‰ Ç Ã Ä ‰ ÈW~stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refÊ ì stmmacethÖ F-G@HSöokay± ‰ †\ ‡ Åsoutput€I‹rgmiiidefault_JKLMN ”O¤ ºN † Ï<Ø/mdio,snps,dwmac-mdio ethernet-phy@0,ethernet-phy-ieee802.3-c22CIstmmac-axi-configáëûCFrx-queues-config CGqueue0tx-queues-config!CHqueue0vop@fe040000 þ0þ@7vopgamma-lut ”( Ý Þ ß à á%~aclkhclkdclk_vp0dclk_vp1dclk_vp2ÓP« Ööokay,rockchip,rk3568-vop± ß à\ ports Cport@0 endpoint@2AQCYport@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? ” Ý Þ ~aclkifaceÚ« öokayCPdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ D ~pclkhclk è Ú�dphyŠR« apbÊ Ö ödisabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ E ~pclkhclk é Ú�dphyŠS« apbÊ Ö ödisabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  -( æ ç “( Ú~iahbisfrcecrefidefault _TUV« zÖQöokaybWrXCports port@0endpointAYCQport@1endpointAZCÑqos@fe128000,rockchip,rk3568-qossysconþ€ C(qos@fe138080,rockchip,rk3568-qossysconþ€€ C7qos@fe138100,rockchip,rk3568-qossysconþ� C8qos@fe138180,rockchip,rk3568-qossysconþ�€ C9qos@fe148000,rockchip,rk3568-qossysconþ€ C)qos@fe148080,rockchip,rk3568-qossysconþ€€ C*qos@fe148100,rockchip,rk3568-qossysconþ� C+qos@fe150000,rockchip,rk3568-qossysconþ C5qos@fe158000,rockchip,rk3568-qossysconþ€ C/qos@fe158100,rockchip,rk3568-qossysconþ� C0qos@fe158180,rockchip,rk3568-qossysconþ�€ C1qos@fe158200,rockchip,rk3568-qossysconþ‚ C2qos@fe158280,rockchip,rk3568-qossysconþ‚€ C3qos@fe158300,rockchip,rk3568-qossysconþƒ C4qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ C:qos@fe190280,rockchip,rk3568-qossysconþ€ C>qos@fe190300,rockchip,rk3568-qossysconþ C?qos@fe190380,rockchip,rk3568-qossysconþ€ C@qos@fe190400,rockchip,rk3568-qossysconþ CAqos@fe198000,rockchip,rk3568-qossysconþ€ C6qos@fe1a8000,rockchip,rk3568-qossysconþ€ C,qos@fe1a8080,rockchip,rk3568-qossysconþ€€ C-qos@fe1a8100,rockchip,rk3568-qossysconþ� C.pcie@fe260000,rockchip,rk3568-pcie0À@þ&ô7dbiapbconfig<KJIHG·syspmcmsglegacyerr‚( � ‚ ƒ „ …$~aclk_mstaclk_slvaclk_dbipclkauxûpciÿŒ`Ÿ[[[[­¾ÍÜëóŠ �pcie-phy«Twôôô ô à@Ê ¡pipe  ödisabledlegacy-interrupt-controllerÿê HC[mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ b  ° ± Š ‹~biuciuciu-driveciu-sampleçòðÑ€Ê Ôresetöokayý !idefault_\]^_,:`Fmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ c  ² ³ Œ �~biuciuciu-driveciu-sampleçòðÑ€Ê Öreset ödisabledspi@fe300000 ,rockchip,sfcþ0@ e x v~clk_sfchclk_sfc_aidefault ödisabledmmc@fe310000,rockchip,rk3568-dwcmshcþ1 ± { }Á ëÂn6( | z y { }~corebusaxiblocktimeröokayýò ëÂSidefault_bcdei2s@fe400000,rockchip,rk3568-i2s-tdmþ@ 4± = AÁFÏqFÏq ? C 9~mclk_txmclk_rxhclkufatxÊ P Q tx-mrx-mÖQöokayCi2s@fe410000,rockchip,rk3568-i2s-tdmþA 5± E IÁFÏqFÏq G K :~mclk_txmclk_rxhclkuffarxtxÊ R S tx-mrx-mÖidefault0_ghijklmnopqrQ ödisabledi2s@fe420000,rockchip,rk3568-i2s-tdmþB 6± MÁFÏq O O ;~mclk_txmclk_rxhclkuffatxrxÊ TmÖidefault_stuvQ ödisabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC 7 S W <~mclk_txmclk_rxhclkuffatxrxÊ U V tx-mrx-mÖQ ödisabledpdm@fe440000,rockchip,rk3568-pdmþD L Z Y~pdm_clkpdm_hclkuf arx_wxyz{|idefaultÊ Xpdm-mQ ödisabledspdif@fe460000,rockchip,rk3568-spdifþF f ~mclkhclk _ \ufatxidefault_}Q ödisableddma-controller@fe530000,arm,pl330arm,primecellþS@ k   ~apb_pclk‚C"dma-controller@fe550000,arm,pl330arm,primecellþU@k   ~apb_pclk‚Cfi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ / H G ~i2cpclk_~idefault  ödisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ 0 J I ~i2cpclk_idefault  ödisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ 1 L K ~i2cpclk_€idefault öokayrtc@51,haoyu,hym8563QŸ Lrtcic_32koutidefault_�pi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] 2 N M ~i2cpclk_‚idefault  ödisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ 3 P O ~i2cpclk_ƒidefault  ödisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` •   ~tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa g R Q~spiclkapb_pclku""atxrxidefault _„…†  ödisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb h T S~spiclkapb_pclku""atxrxidefault _‡ˆ‰  ödisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc i V U~spiclkapb_pclku""atxrxidefault _Š‹Œ  ödisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd j X W~spiclkapb_pclku""atxrxidefault_�  ödisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe u  ~baudclkapb_pclku""_Židefaultz‡ ödisabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf v #  ~baudclkapb_pclku""_�idefaultz‡öokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg w ' $~baudclkapb_pclku""_�idefaultz‡ ödisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh x + (~baudclkapb_pclku"" _‘idefaultz‡ ödisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi y / ,~baudclkapb_pclku" " _’idefaultz‡ ödisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj z 3 0~baudclkapb_pclku" " _“idefaultz‡ ödisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk { 7 4~baudclkapb_pclku""_”idefaultz‡ ödisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl | ; 8~baudclkapb_pclku""_•idefaultz‡ ödisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm } ? <~baudclkapb_pclku""_–idefaultz‡ ödisabledthermal-zonescpu-thermal�d£è±—tripscpu_alert0ÁpÍÐpassiveC˜cpu_alert1Á$øÍÐpassivecpu_critÁsÍÐ criticalcooling-mapsmap0ؘ0Ýÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal�£è±—tripsgpu-thresholdÁpÍÐpassivegpu-targetÁ$øÍÐpassiveC™gpu-critÁsÍÐ criticalcooling-mapsmap0Ø™ Ýšÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq s±  Áf@ ®`  ~tsadcapb_pclkÊ � ‚ ×Öìsiinitdefaultsleep_› œ › öokay - DC—saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr ]  ~saradcapb_pclkÊ € saradc-apb _öokay q�pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn Z Y ~pwmpclk_židefault‘ ödisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn Z Y ~pwmpclk_Ÿidefault‘ ödisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn  Z Y ~pwmpclk_ idefault‘ ödisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0 Z Y ~pwmpclk_¡idefault‘ ödisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ] \ ~pwmpclk_¢idefault‘öokaypwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ] \ ~pwmpclk_£idefault‘ ödisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo  ] \ ~pwmpclk_¤idefault‘ ödisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0 ] \ ~pwmpclk_¥idefault‘ ödisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp ` _ ~pwmpclk_¦idefault‘ ödisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp ` _ ~pwmpclk_§idefault‘ ödisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp  ` _ ~pwmpclk_¨idefault‘ ödisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0 ` _ ~pwmpclk_©idefault‘ ödisabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ " }  ~refapbpipe±"ÁõáÊ Ç }ª �« ¥öokayCphy@fe840000,rockchip,rk3568-naneng-combphyþ„ % ~  ~refapbpipe±%ÁõáÊ É }ª �¬ ¥öokayCphy@fe870000,rockchip,rk3568-csi-dphyþ‡ y~pclk ¥Ê ºapbÖ ödisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ… ~refpclk  z ¥« apbÊ » ödisabledCRmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ† ~refpclk  { ¥« apbÊ ¼ ödisabledCSusb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠ ~phyclkLclk_usbphy0_480m ‡ °­Ÿöokayhost-port ¥öokay À®Cotg-port ¥öokay À¯Cusb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹ ~phyclkLclk_usbphy1_480m ˆ °°Ÿöokayhost-port ¥öokayCotg-port ¥öokayCpinctrl,rockchip,rk3568-pinctrlÖ ˱ wgpio@fdd60000,rockchip,gpio-bankýÖ ! .  Ø èêÿCgpio@fe740000,rockchip,gpio-bankþt " c d Ø èêÿgpio@fe750000,rockchip,gpio-bankþu # e f Ø èêÿCÃgpio@fe760000,rockchip,gpio-bankþv $ g h Ø èêÿCOgpio@fe770000,rockchip,gpio-bankþw % i j Ø èêÿpcfg-pull-up ôC´pcfg-pull-none C²pcfg-pull-none-drv-level-1  C¶pcfg-pull-none-drv-level-2  Cµpcfg-pull-none-drv-level-3  C¹pcfg-pull-none-drv-level-5  Cºpcfg-pull-up-drv-level-1 ô C¸pcfg-pull-up-drv-level-2 ô C³pcfg-pull-none-smt  C·acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 2²C cpuebcedpdpemmcemmc-bus8€ 2 ³ ³³³³³³³Cbemmc-clk 2³Ccemmc-cmd 2³Cdemmc-datastrobe 2²Ceeth0eth1flashfspifspi-pins` 2²²²²²²Cagmac0gmac0-miim 2²²CÈgmac0-rx-bus20 2²²²CÊgmac0-tx-bus20 2 µ µ ²CÉgmac0-rgmii-clk 2²¶CËgmac0-rgmii-bus@ 2²²µµCÌgmac1gmac1m1-miim 2²²CJgmac1m1-rx-bus20 2²² ²CLgmac1m1-tx-bus20 2µµ²CKgmac1m1-rgmii-clk 2²¶CMgmac1m1-rgmii-bus@ 2²²µµCNgpuhdmitxhdmitxm0-cec 2²CVhdmitx-scl 2²CThdmitx-sda 2²CUi2c0i2c0-xfer 2 · ·Ci2c1i2c1-xfer 2 · ·C~i2c2i2c2m0-xfer 2 ··Ci2c3i2c3m0-xfer 2··C€i2c4i2c4m0-xfer 2 · ·C‚i2c5i2c5m0-xfer 2 · ·Cƒi2s1i2s1m0-lrckrx 2²Cji2s1m0-lrcktx 2²Cii2s1m0-sclkrx 2²Chi2s1m0-sclktx 2²Cgi2s1m0-sdi0 2 ²Cki2s1m0-sdi1 2 ²Cli2s1m0-sdi2 2 ²Cmi2s1m0-sdi3 2²Cni2s1m0-sdo0 2²Coi2s1m0-sdo1 2²Cpi2s1m0-sdo2 2 ²Cqi2s1m0-sdo3 2 ²Cri2s2i2s2m0-lrcktx 2²Cti2s2m0-sclktx 2²Csi2s2m0-sdi 2²Cui2s2m0-sdo 2²Cvi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk 2²Cwpdmm0-clk1 2²Cxpdmm0-sdi0 2 ²Cypdmm0-sdi1 2 ²Czpdmm0-sdi2 2 ²C{pdmm0-sdi3 2²C|pmicpmic_int 2´C pmupwm0pwm0m0-pins 2²C$pwm1pwm1m0-pins 2²C%pwm2pwm2m0-pins 2²C&pwm3pwm3-pins 2²C'pwm4pwm4-pins 2²Cžpwm5pwm5-pins 2²CŸpwm6pwm6-pins 2²C pwm7pwm7-pins 2²C¡pwm8pwm8m0-pins 2 ²C¢pwm9pwm9m0-pins 2 ²C£pwm10pwm10m0-pins 2 ²C¤pwm11pwm11m0-pins 2²C¥pwm12pwm12m1-pins 2²C¦pwm13pwm13m1-pins 2²C§pwm14pwm14m1-pins 2²C¨pwm15pwm15m1-pins 2²C©refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ 2³³³³C\sdmmc0-clk 2³C]sdmmc0-cmd 2³C^sdmmc0-det 2´C_sdmmc1sdmmc2spdifspdifm0-tx 2²C}spi0spi0m0-pins0 2 ²²²C†spi0m0-cs0 2²C„spi0m0-cs1 2²C…spi1spi1m0-pins0 2 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“stmmac-axi-configáëûCÅrx-queues-config CÆqueue0tx-queues-config!CÇqueue0fixed-linkåè ‡ “phy@fe820000,rockchip,rk3568-naneng-combphyþ‚  |  ~refapbpipe±ÁõáÊ Å }ª �Î ¥öokayCchosen ™serial2:1500000n8leds ,gpio-ledsidefault_ÏÐled-0 ¥ «off ¹status led-1 ¥ «on ¹power dc-12v-regulator,regulator-fixed~dc_12v�¡ã·û·CÒhdmi-con,hdmi-connectoraportendpointAÑCZvcc3v3-sys-regulator,regulator-fixed ~vcc3v3_sys�¡ã2Z û2Z  ÂÒC!vcc5v0-sys-regulator,regulator-fixed ~vcc5v0_sys�¡ãLK@ûLK@ ÂÒCÓpcie30-avdd0v9-regulator,regulator-fixed~pcie30_avdd0v9�¡ã » û »  Â!pcie30-avdd1v8-regulator,regulator-fixed~pcie30_avdd1v8�¡ãw@ûw@ Â!vcc3v3-pi6c-05-regulator,regulator-fixed ~vcc3v3_pcieã2Z û2Z  Í  à @ ÂÓC¼vcc3v3-minipcie-regulator,regulator-fixed~vcc3v3_minipcieã2Z û2Z  Í Ÿidefault_Ô àÃP ¼CÄvcc3v3-ngff-regulator,regulator-fixed ~vcc3v3_ngffã2Z û2Z  Í Ÿidefault_Õ àÃP ¼CÀvcc5v0-usb-regulator,regulator-fixed ~vcc5v0_usb�¡ãLK@ûLK@ ÂÒC×vcc5v0-usb-host-regulator,regulator-fixed Í Ÿidefault_Ö~vcc5v0_usb_hostãLK@ûLK@ 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interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellsenable-methodoperating-points-v2phandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesrockchip,grfrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-nameregulator-always-onregulator-boot-onregulator-init-microvoltregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsfifo-depthmax-frequencyreset-namessnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoassigned-clock-parentsclock_in_outphy-handlephy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaysnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplybus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplynon-removabledma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplyrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfdata-lanesreset-gpiosvpcie3v3-supplylabelethernetfull-duplexpausestdout-pathcolordefault-statefunctionvin-supplyenable-active-highstartup-delay-us