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ZdisabledZams_pl@400xlnx,zynqmp-ams-pl ZdisabledZ dma-controller@fd4c0000xlnx,zynqmp-dpdmaZokayZýL &z¡axi_clkÒ )ànÜdisplay@fd4a0000xlnx,zynqmp-dpsub-1.7Zokay@ZýJýJ ýJ°ýJÀDdpblendav_bufaud &w*¡dp_apb_clkdp_aud_clkdp_vtc_pixel_clk_inÒ )'Îvid0vid1vid2gfx0 Ønpss_ref_clk fixed-clock”jü UÜvideo_clk fixed-clock”j›üÀÜpss_alt_ref_clk fixed-clock”jÜgt_crx_ref_clk fixed-clock”joóÜ aux_ref_clk fixed-clock”j›üÀÜ aliasesÝ/axi/ethernet@ff0b0000ç/axi/ethernet@ff0c0000ñ/axi/ethernet@ff0d0000û/axi/ethernet@ff0e0000/axi/i2c@ff020000 /axi/i2c@ff030000/axi/rtc@ffa60000/axi/serial@ff000000/axi/serial@ff010000$/axi/spi@ff0f0000chosen )earlycon2serial0:115200n8memory@0,memory Z€€ compatible#address-cells#size-cellsmodeldevice_typeenable-methodoperating-points-v2regcpu-idle-statesclocksentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usphandleopp-sharedopp-hzopp-microvoltclock-latency-nsinterrupt-parentinterruptsxlnx,ipi-idrangesreg-names#mbox-cellsstatus#power-domain-cellsmboxesmbox-names#reset-cells#clock-cellsclock-namesfpga-mgrtx-fifo-depthrx-fifo-depthpower-domains#dma-cellsxlnx,bus-widthiommus#interrupt-cellsinterrupt-controllerresetsreset-namesphy-modephy-handle#gpio-cellsgpio-controllerclock-frequencymsi-controllerinterrupt-namesmsi-parentbus-rangeinterrupt-map-maskinterrupt-mapnum-csspi-tx-bus-widthspi-rx-bus-widthspi-max-frequency#phy-cellscalibrationclock-output-names#iommu-cells#global-interruptstimer-widthsnps,quirk-frame-length-adjustmentsnps,resume-hs-terminationstimeout-secreset-on-timeout#io-channel-cellsdma-namesdmasethernet0ethernet1ethernet2ethernet3i2c0i2c1rtc0serial0serial1spi0bootargsstdout-path