Ð þíLê8Iœ(NId ,Freescale i.MX8QM MEK2fsl,imx8qm-mekfsl,imx8qmaliases=/bus@5b000000/mmc@5b010000B/bus@5b000000/mmc@5b020000G/bus@5b000000/mmc@5b030000L/bus@5a000000/serial@5a060000T/bus@5a000000/serial@5a070000\/bus@5a000000/serial@5a080000d/bus@5a000000/serial@5a090000cpus cpu@0lcpu2arm,cortex-a53x|psciŠ€—@©¶€Ã@Õ€âcpu@1lcpu2arm,cortex-a53x|psciŠ€—@©¶€Ã@Õ€âcpu@2lcpu2arm,cortex-a53x|psciŠ€—@©¶€Ã@Õ€âcpu@3lcpu2arm,cortex-a53x|psciŠ€—@©¶€Ã@Õ€âl2-cache02cacheóŒ™@«ÿl2-cache12cacheóŒ™@«interrupt-controller@51a00000 2arm,gic-v3PxQ Q° R RR - ÿpmu2arm,armv8-pmuv3 -psci 2arm,psci-1.0ƒsmctimer2arm,armv8-timer0-   system-controller 2fsl,imx-scu 8tx0rx0gip3$Cpower-controller2fsl,imx8qm-scu-pdfsl,scu-pdJÿclock-controller2fsl,imx8qm-clkfsl,scu-clk^ÿ pinctrl2fsl,imx8qm-iomuxcfec1grp¨k¦ ¥ ô ó õ ö ÷ ø ù ú û ü ý þ ÿlpuart0grpk  ÿ usdhc1grp„kÑAÒ!Ó!Ô!Õ!Ö!×!Ø!Ù!Ú!ÛAÿusdhc2grpTkÞAß!à!á!ã!ä!Ÿ!ÿrtc2fsl,imx8qxp-sc-rtcbus@58000000 2simple-bus tXXclock-img-ipg 2fixed-clock^{ ë ‹img_ipg_clkÿjpegdec@58400000xX@0-5678ž¥peripg±Á ë ëÂ(Ö�‚ƒ„%2nxp,imx8qm-jpgdecnxp,imx8qxp-jpgdecjpegenc@58450000xXE0-1234ž¥peripg±Á ë ëÂ(Ö…†‡ˆ%2nxp,imx8qm-jpgdecnxp,imx8qxp-jpgencclock-controller@585d00002fsl,imx8qxp-lpcgxX]^žä0‹img_jpeg_dec_lpcg_clkimg_jpeg_dec_lpcg_ipg_clkÖÿclock-controller@585f00002fsl,imx8qxp-lpcgxX_^žä0‹img_jpeg_enc_lpcg_clkimg_jpeg_enc_lpcg_ipg_clkÖÿbus@5a000000 2simple-bus tZZclock-dma-ipg 2fixed-clock^{' ‹dma_ipg_clkÿserial@5a060000xZ -áž ¥ipgbaudÖ9òokay%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartùdefault serial@5a070000xZ -âž   ¥ipgbaudÖ: òdisabled%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartserial@5a080000xZ -ãž   ¥ipgbaudÖ; òdisabled%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartserial@5a090000xZ  -äž   ¥ipgbaudÖ< òdisabled%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartclock-controller@5a4600002fsl,imx8qxp-lpcgxZF^ž 9ä'‹uart0_lpcg_baud_clkuart0_lpcg_ipg_clkÖ9ÿclock-controller@5a4700002fsl,imx8qxp-lpcgxZG^ž :ä'‹uart1_lpcg_baud_clkuart1_lpcg_ipg_clkÖ:ÿ clock-controller@5a4800002fsl,imx8qxp-lpcgxZH^ž ;ä'‹uart2_lpcg_baud_clkuart2_lpcg_ipg_clkÖ;ÿ clock-controller@5a4900002fsl,imx8qxp-lpcgxZI^ž <ä'‹uart3_lpcg_baud_clkuart3_lpcg_ipg_clkÖ<ÿ i2c@5a800000xZ€@ -Üž¥peripg ± `Án6Ö` òdisabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2ci2c@5a810000xZ�@ -Ýž¥peripg ± aÁn6Öa òdisabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2ci2c@5a820000xZ‚@ -Þž¥peripg ± bÁn6Öb òdisabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2ci2c@5a830000xZƒ@ -ßž¥peripg ± cÁn6Öc òdisabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2cclock-controller@5ac000002fsl,imx8qxp-lpcgxZÀ^ž `ä ‹i2c0_lpcg_clki2c0_lpcg_ipg_clkÖ`ÿclock-controller@5ac100002fsl,imx8qxp-lpcgxZÁ^ž aä ‹i2c1_lpcg_clki2c1_lpcg_ipg_clkÖaÿclock-controller@5ac200002fsl,imx8qxp-lpcgxZÂ^ž bä ‹i2c2_lpcg_clki2c2_lpcg_ipg_clkÖbÿclock-controller@5ac300002fsl,imx8qxp-lpcgxZÃ^ž cä ‹i2c3_lpcg_clki2c3_lpcg_ipg_clkÖcÿclock-controller@5a4a00002fsl,imx8qxp-lpcgxZJ^ž =ä'‹uart4_lpcg_baud_clkuart4_lpcg_ipg_clkÖ=bus@5b000000 2simple-bus t[[clock-conn-axi 2fixed-clock^{ÞCU ‹conn_axi_clkÿclock-conn-ahb 2fixed-clock^{ ï!ª ‹conn_ahb_clkclock-conn-ipg 2fixed-clock^{÷�Õ ‹conn_ipg_clkÿmmc@5b010000 -èx[ž ¥ipgahbperÖøòokay32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhcùdefault!)mmc@5b020000 -éx[ž ¥ipgahbperÖù7Lòokay32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhcùdefault\ h qmmc@5b030000 -êx[ž ¥ipgahbperÖú òdisabled32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhcethernet@5b040000x[0- ž ¥ipgahbenet_clk_refptp± û ûÁæ²€sY@zŒÖûòokay2fsl,imx8qm-fecfsl,imx6sx-fecùdefault žrgmii-id§²mdio ethernet-phy@02ethernet-phy-ieee802.3-c22xÿethernet-phy@12ethernet-phy-ieee802.3-c22xethernet@5b050000x[0- ž ¥ipgahbenet_clk_refptp± ü üÁæ²€sY@zŒÖü òdisabled2fsl,imx8qm-fecfsl,imx6sx-fecclock-controller@5b2000002fsl,imx8qxp-lpcgx[ ^ž ø ä9‹sdhc0_lpcg_per_clksdhc0_lpcg_ipg_clksdhc0_lpcg_ahb_clkÖøÿclock-controller@5b2100002fsl,imx8qxp-lpcgx[!^ž ù ä9‹sdhc1_lpcg_per_clksdhc1_lpcg_ipg_clksdhc1_lpcg_ahb_clkÖùÿclock-controller@5b2200002fsl,imx8qxp-lpcgx["^ž ú ä9‹sdhc2_lpcg_per_clksdhc2_lpcg_ipg_clksdhc2_lpcg_ahb_clkÖúÿclock-controller@5b2300002fsl,imx8qxp-lpcgx[#^0ž û û ûä …‹enet0_lpcg_timer_clkenet0_lpcg_txc_sampling_clkenet0_lpcg_ahb_clkenet0_lpcg_rgmii_txc_clkenet0_lpcg_ipg_clkenet0_lpcg_ipg_s_clkÖûÿclock-controller@5b2400002fsl,imx8qxp-lpcgx[$^0ž ü ü üä …‹enet1_lpcg_timer_clkenet1_lpcg_txc_sampling_clkenet1_lpcg_ahb_clkenet1_lpcg_rgmii_txc_clkenet1_lpcg_ipg_clkenet1_lpcg_ipg_s_clkÖüÿbus@5d000000 2simple-bus t]]clock-lsio-mem 2fixed-clock^{ ë ‹lsio_mem_clkclock-lsio-bus 2fixed-clock^{õá ‹lsio_bus_clkÿ gpio@5d080000x] -ˆÃÓÖÇ2fsl,imx8qm-gpiofsl,imx35-gpiogpio@5d090000x]  -‰ÃÓÖÈ2fsl,imx8qm-gpiofsl,imx35-gpiogpio@5d0a0000x]  -ŠÃÓÖÉ2fsl,imx8qm-gpiofsl,imx35-gpiogpio@5d0b0000x]  -‹ÃÓÖÊ2fsl,imx8qm-gpiofsl,imx35-gpiogpio@5d0c0000x]  -ŒÃÓÖË2fsl,imx8qm-gpiofsl,imx35-gpioÿgpio@5d0d0000x]  -�ÃÓÖÌ2fsl,imx8qm-gpiofsl,imx35-gpiogpio@5d0e0000x] -ŽÃÓÖÍ2fsl,imx8qm-gpiofsl,imx35-gpiogpio@5d0f0000x] -�ÃÓÖÎ2fsl,imx8qm-gpiofsl,imx35-gpiomailbox@5d1b0000x] -°ß òdisabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1c0000x] -±ß,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-muÿmailbox@5d1d0000x] -²ß òdisabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1e0000x] -³ß òdisabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1f0000x] -´ß òdisabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d200000x]  -¸ßÖÚ òdisabled2fsl,imx8qm-mufsl,imx6sx-mumailbox@5d210000x]! -¹ßÖÛ òdisabled2fsl,imx8qm-mufsl,imx6sx-mumailbox@5d280000x]( -ÀßÖâ2fsl,imx8qm-mufsl,imx6sx-muclock-controller@5d4000002fsl,imx8qxp-lpcgx]@^4ž ¿ ¿ ¿ ¿äh‹pwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clkÖ¿clock-controller@5d4100002fsl,imx8qxp-lpcgx]A^4ž À À À Àäh‹pwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clkÖÀclock-controller@5d4200002fsl,imx8qxp-lpcgx]B^4ž Á Á Á Áäh‹pwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clkÖÁclock-controller@5d4300002fsl,imx8qxp-lpcgx]C^4ž    Âäh‹pwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clkÖÂclock-controller@5d4400002fsl,imx8qxp-lpcgx]D^4ž à à à Ãäh‹pwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clkÖÃclock-controller@5d4500002fsl,imx8qxp-lpcgx]E^4ž Ä Ä Ä Ääh‹pwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clkÖÄclock-controller@5d4600002fsl,imx8qxp-lpcgx]F^4ž Å Å Å Åäh‹pwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clkÖÅclock-controller@5d4700002fsl,imx8qxp-lpcgx]G^4ž Æ Æ Æ Æäh‹pwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clkÖÆchosenë/bus@5a000000/serial@5a060000memory@80000000lmemoryx€@usdhc2-vmmc2regulator-fixed ÷SD1_SPWR-ÆÀ-ÆÀ 6;ÿ interrupt-parent#address-cells#size-cellsmodelcompatiblemmc0mmc1mmc2serial0serial1serial2serial3device_typeregenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecache-levelphandle#interrupt-cellsinterrupt-controllerinterruptsmbox-namesmboxes#power-domain-cells#clock-cellsfsl,pinsrangesclock-frequencyclock-output-namesclocksclock-namesassigned-clocksassigned-clock-ratespower-domainsclock-indicesstatuspinctrl-namespinctrl-0bus-widthno-sdno-sdionon-removablefsl,tuning-start-tapfsl,tuning-stepvmmc-supplycd-gpioswp-gpiosfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetgpio-controller#gpio-cells#mbox-cellsstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltgpioenable-active-high