Ð þíëo8àL( #à ',friendlyarm,nanopi-r5crockchip,rk35687FriendlyElec NanoPi R5Caliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/mmc@fe2b0000â/mmc@fe310000cpus cpu@0çcpu,arm,cortex-a55ó÷þ psci/€<@N€[€h@z€‡˜£ cpu@100çcpu,arm,cortex-a55óþ psci/€<@N€[€h@z€‡˜£ cpu@200çcpu,arm,cortex-a55óþ psci/€<@N€[€h@z€‡˜£ cpu@300çcpu,arm,cortex-a55óþ psci/€<@N€[€h@z€‡˜£ l3-cache,cache«·1>@P£opp-table-0,operating-points-v2Å£opp-408000000ÐQ– × »  » Œ0åœ@opp-600000000Ð#ÃF × »  » Œ0opp-816000000Ð0£, × »  » Œ0öopp-1104000000ÐAÍ´ × »  » Œ0opp-1416000000ÐTfr × »  » Œ0opp-1608000000Ð_Ø" ×à˜à˜Œ0opp-1800000000ÐkIÒ ×��Œ0opp-1992000000Ðv»‚ ׌0Œ0Œ0display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc‚ protocol@14ó£opp-table-1,operating-points-v2£Fopp-200000000Ð ëÂ × øP øPB@opp-300000000Ðá£ × øP øPB@opp-400000000Ðׄ × øP øPB@opp-600000000Ð#ÃF × »  » B@opp-700000000Ð)¹' ×~ð~ðB@opp-800000000Ð/¯ ×B@B@B@hdmi-sound,simple-audio-card&HDMI=i2sVpokaysimple-audio-card,codecwsimple-audio-card,cpuw pmu,arm,cortex-a55-pmu0�äåæçŒ psci ,arm,psci-1.0smctimer,arm,armv8-timer0�   Ÿxin24m ,fixed-clock¶n6Æxin24m£xin32k ,fixed-clock¶€Æxin32kÙãdefaultsram@10f000 ,mmio-sramóð ñðsram@0,arm,scmi-shmemó£sata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcióü@÷›œ�øsatapmaliverxoob �_  sata-phy% pdisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcióü€÷ ¡¢øsatapmaliverxoob �`  sata-phy% pdisabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3óüÀ@ �©÷¦§¥øref_clksuspend_clkbus_clk3host ;utmi_wide%D”Kpokay  usb2-phyusb3-phydusb@fd000000,rockchip,rk3568-dwc3snps,dwc3óý@ �ª÷©ª¨øref_clksuspend_clkbus_clk3host  usb2-phyusb3-phy ;utmi_wide%D•Kpokayinterrupt-controller@fd400000 ,arm,gic-v3 óý@ýF � k€‘ýA›(¦£usb@fd800000 ,generic-ehcióý€ �‚÷½¾¼ usbpokayusb@fd840000 ,generic-ohcióý„ �ƒ÷½¾¼ usbpokayusb@fd880000 ,generic-ehcióýˆ �…÷¿À¼ usbpokayusb@fd8c0000 ,generic-ohcióýŒ �†÷¿À¼ usbpokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdóý£Xio-domains&,rockchip,rk3568-pmu-io-voltage-domainpokayµÃÑßíû syscon@fdc50000óýÅ ,rockchip,rk3568-pipe-grfsyscon£«syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdóýÆ£ syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconóýÈ£¬syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconóýÉ£­syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconóýÊ€£®syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconóýÊ€€£°clock-controller@fdd00000,rockchip,rk3568-pmucruóýÐ%£clock-controller@fdd20000,rockchip,rk3568-cruóýÒ÷øxin24m%2 B€G†Œ ëÂWn £i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cóýÔ �.÷- øi2cpclkÙ!ãdefault pokayregulator@1c ,tcs,tcs4525ó{˜vdd_cpu§»Í 5åŒ0ýü"£regulator-state-mempmic@20,rockchip,rk809ó #�ãdefaultÙ$6W%c%o%{%‡%“%Ÿ%«%·%ÃregulatorsDCDC_REG1 ˜vdd_logic§»ÑÍ¡ å™pýqregulator-state-memDCDC_REG2˜vdd_gpu§ÑÍ¡ å™pýq£Gregulator-state-memDCDC_REG3˜vcc_ddr§»Ñregulator-state-memèDCDC_REG4˜vdd_npuÑÍ¡ å™pýqregulator-state-memDCDC_REG5˜vcc_1v8§»Íw@åw@£regulator-state-memLDO_REG1˜vdda0v9_imageÍ~ðå~ð£Tregulator-state-memLDO_REG2 ˜vdda_0v9§»Í » å » regulator-state-memLDO_REG3 ˜vdda0v9_pmu§»Í » å » regulator-state-memè » LDO_REG4 ˜vccio_acodecÍ2Z å2Z £regulator-state-memLDO_REG5 ˜vccio_sdÍw@å2Z £regulator-state-memLDO_REG6 ˜vcc3v3_pmu§»Í2Z å2Z £regulator-state-memè2Z LDO_REG7 ˜vcca_1v8§»Íw@åw@£žregulator-state-memLDO_REG8 ˜vcca1v8_pmu§»Íw@åw@regulator-state-memèw@LDO_REG9˜vcca1v8_imageÍw@åw@£Uregulator-state-memSWITCH_REG1˜vcc_3v3§»£regulator-state-memSWITCH_REG2 ˜vcc3v3_sd§»£\regulator-state-memserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartóýÕ �t÷ ,øbaudclkapb_pclk&&Ù'ãdefault!. pdisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmóý×÷ 0 øpwmpclkÙ(ãdefault8 pdisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmóý×÷ 0 øpwmpclkÙ)ãdefault8 pdisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmóý× ÷ 0 øpwmpclkÙ*ãdefault8 pdisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmóý×0÷ 0 øpwmpclkÙ+ãdefault8 pdisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdóýÙpower-controller!,rockchip,rk3568-power-controllerC £power-domain@7ó÷W,Cpower-domain@8ó÷ÌÍ W-./Cpower-domain@9ó ÷ÚÛÜ W012Cpower-domain@10ó ÷ñòW345678Cpower-domain@11ó ÷íW9Cpower-domain@13÷ó W:Cpower-domain@14ó÷ W;<=Cpower-domain@15ó÷ W>?@ABCDECgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostóýæ@$�()' ^jobmmugpu÷øgpubusþF%pokaynG£›video-codec@fdea0400,rockchip,rk3568-vpuóýê �‹^vdpu÷îï øaclkhclkzH% iommu@fdea0800,rockchip,rk3568-iommuóýê@ �Š øaclkiface÷îï% �£Hrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaóýë€ �Z÷óôõøaclkhclksclkD&$% Žcoreaxiahb% video-codec@fdee0000,rockchip,rk3568-vepuóýî �@÷ýþ øaclkhclkzI% iommu@fdee0800,rockchip,rk3568-iommuóýî@ �?÷ýþ øaclkiface% �£Immc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcóþ@ �d ÷ÁÂŽ�øbiuciuciu-driveciu-sampleš¥ðÑ€DëŽreset pdisabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aóþ� ^macirqeth_wake_irq@÷†‰‰ÇÃĉÈWøstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refDì Žstmmacethn ³JÃÔKçLú pdisabledmdio,snps,dwmac-mdio stmmac-axi-config £Jrx-queues-config-£Kqueue0tx-queues-configC£Lqueue0vop@fe040000 óþ0þ@Yvopgamma-lut �”(÷ÝÞßàá%øaclkhclkdclk_vp0dclk_vp1dclk_vp2zM% n pokay,rockchip,rk3568-vop2ßàWports £port@0ó endpoint@2ócN£Vport@1ó port@2ó iommu@fe043e00,rockchip,rk3568-iommu óþ>þ? �”÷ÝÞ øaclkiface�% pokay£Mdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsióþ �Døpclk÷è dphyO% ŽapbDn  pdisabledports port@0óport@1ódsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsióþ �Eøpclk÷é dphyP% ŽapbDn  pdisabledports port@0óport@1óhdmi@fe0a0000,rockchip,rk3568-dw-hdmióþ  �-(÷æç“(Úøiahbisfrcecrefãdefault ÙQRS% !n spokay„T”U£ports port@0óendpointcV£Nport@1óendpointcW£Çqos@fe128000,rockchip,rk3568-qossysconóþ€ £,qos@fe138080,rockchip,rk3568-qossysconóþ€€ £;qos@fe138100,rockchip,rk3568-qossysconóþ� £<qos@fe138180,rockchip,rk3568-qossysconóþ�€ £=qos@fe148000,rockchip,rk3568-qossysconóþ€ £-qos@fe148080,rockchip,rk3568-qossysconóþ€€ £.qos@fe148100,rockchip,rk3568-qossysconóþ� £/qos@fe150000,rockchip,rk3568-qossysconóþ £9qos@fe158000,rockchip,rk3568-qossysconóþ€ £3qos@fe158100,rockchip,rk3568-qossysconóþ� £4qos@fe158180,rockchip,rk3568-qossysconóþ�€ £5qos@fe158200,rockchip,rk3568-qossysconóþ‚ £6qos@fe158280,rockchip,rk3568-qossysconóþ‚€ £7qos@fe158300,rockchip,rk3568-qossysconóþƒ £8qos@fe180000,rockchip,rk3568-qossysconóþ qos@fe190000,rockchip,rk3568-qossysconóþ £>qos@fe190280,rockchip,rk3568-qossysconóþ€ £Bqos@fe190300,rockchip,rk3568-qossysconóþ £Cqos@fe190380,rockchip,rk3568-qossysconóþ€ £Dqos@fe190400,rockchip,rk3568-qossysconóþ £Eqos@fe198000,rockchip,rk3568-qossysconóþ€ £:qos@fe1a8000,rockchip,rk3568-qossysconóþ€ £0qos@fe1a8080,rockchip,rk3568-qossysconóþ€€ £1qos@fe1a8100,rockchip,rk3568-qossysconóþ� £2dfi@fe230000,rockchip,rk3568-dfióþ# � ¤Xpcie@fe260000,rockchip,rk3568-pcie0óÀ@þ&ôYdbiapbconfig<�KJIHG^syspmcmsglegacyerr±(÷�‚ƒ„…$øaclk_mstaclk_slvaclk_dbipclkauxçpci€»`ÎYYYYÜíü "  pcie-phy%Tñôôô ô à@@D¡Žpipe pokayãdefaultÙZ ,[legacy-interrupt-controller€k �H£Ymmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcóþ+@ �b ÷°±Š‹øbiuciuciu-driveciu-sampleš¥ðÑ€DÔŽresetpokay8@GQct\‹ãdefaultÙ]^_`mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcóþ,@ �c ÷²³Œ�øbiuciuciu-driveciu-sampleš¥ðÑ€DÖŽreset pdisabledspi@fe300000 ,rockchip,sfcóþ0@ �e÷xvøclk_sfchclk_sfcÙaãdefault pdisabledmmc@fe310000,rockchip,rk3568-dwcmshcóþ1 �2{}B ëÂn6(÷|zy{}øcorebusaxiblocktimerpokayG¥ ë˜ãdefault Ùbcdrng@fe388000,rockchip,rk3568-rngóþ8€@÷po øcoreahbDmpokayi2s@fe400000,rockchip,rk3568-i2s-tdmóþ@ �42=ABFÏqFÏq÷?C9ømclk_txmclk_rxhclke¦txDPQ Žtx-mrx-mn spokay£ i2s@fe410000,rockchip,rk3568-i2s-tdmóþA �52EIBFÏqFÏq÷GK:ømclk_txmclk_rxhclkee¦rxtxDRS Žtx-mrx-mn ãdefault0Ùfghijklmnopqs pdisabledi2s@fe420000,rockchip,rk3568-i2s-tdmóþB �62MBFÏq÷OO;ømclk_txmclk_rxhclkee¦txrxDTŽtx-mn ãdefaultÙrstus pdisabledi2s@fe430000,rockchip,rk3568-i2s-tdmóþC �7÷SW<ømclk_txmclk_rxhclkee¦txrxDUV Žtx-mrx-mn s pdisabledpdm@fe440000,rockchip,rk3568-pdmóþD �L÷ZYøpdm_clkpdm_hclke ¦rxÙvwxyz{ãdefaultDXŽpdm-ms pdisabledspdif@fe460000,rockchip,rk3568-spdifóþF �f ømclkhclk÷_\e¦txãdefaultÙ|s pdisableddma-controller@fe530000,arm,pl330arm,primecellóþS@� °÷  øapb_pclkÇ£&dma-controller@fe550000,arm,pl330arm,primecellóþU@�°÷  øapb_pclkÇ£ei2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþZ �/÷HG øi2cpclkÙ}ãdefault  pdisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ[ �0÷JI øi2cpclkÙ~ãdefault  pdisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ\ �1÷LK øi2cpclkÙãdefault  pdisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ] �2÷NM øi2cpclkÙ€ãdefault  pdisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ^ �3÷PO øi2cpclkÙ�ãdefault pokayrtc@51,haoyu,hym8563óQ#� Ærtcic_32koutãdefaultÙ‚Ãwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtóþ` �•÷ øtclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spióþa �g÷RQøspiclkapb_pclk&&¦txrxãdefault Ùƒ„…  pdisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spióþb �h÷TSøspiclkapb_pclk&&¦txrxãdefault Ù†‡ˆ  pdisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spióþc �i÷VUøspiclkapb_pclk&&¦txrxãdefault Ù‰Š‹  pdisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spióþd �j÷XWøspiclkapb_pclk&&¦txrxãdefault ÙŒ�Ž  pdisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartóþe �u÷øbaudclkapb_pclk&&Ù�ãdefault!. pdisabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartóþf �v÷# øbaudclkapb_pclk&&Ù�ãdefault!.pokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartóþg �w÷'$øbaudclkapb_pclk&&Ù‘ãdefault!. pdisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartóþh �x÷+(øbaudclkapb_pclk&& Ù’ãdefault!. pdisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartóþi �y÷/,øbaudclkapb_pclk& & Ù“ãdefault!. pdisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartóþj �z÷30øbaudclkapb_pclk& & Ù”ãdefault!. pdisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartóþk �{÷74øbaudclkapb_pclk&&Ù•ãdefault!. pdisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartóþl �|÷;8øbaudclkapb_pclk&&Ù–ãdefault!. pdisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartóþm �}÷?<øbaudclkapb_pclk&&Ù—ãdefault!. pdisabledthermal-zonescpu-thermalÒdèèö˜tripscpu_alert0 p Ðîpassive£™cpu_alert1 $ø Ðîpassivecpu_crit s Ð îcriticalcooling-mapsmap0 ™0 " ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermalÒèèö˜tripsgpu-threshold p Ðîpassivegpu-target $ø Ðîpassive£šgpu-crit s Ð îcriticalcooling-mapsmap0 š "›ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcóþq �s2Bf@ ®`÷øtsadcapb_pclkD�‚×n  1sãdefaultsleepÙœ H� Rpokay h £˜saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcóþr �]÷øsaradcapb_pclkD€ Žsaradc-apb špokay ¬žpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþn÷ZY øpwmpclkÙŸãdefault8 pdisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþn÷ZY øpwmpclkÙ ãdefault8 pdisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþn ÷ZY øpwmpclkÙ¡ãdefault8 pdisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþn0÷ZY øpwmpclkÙ¢ãdefault8 pdisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþo÷]\ øpwmpclkÙ£ãdefault8 pdisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþo÷]\ øpwmpclkÙ¤ãdefault8 pdisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþo ÷]\ øpwmpclkÙ¥ãdefault8 pdisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþo0÷]\ øpwmpclkÙ¦ãdefault8 pdisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþp÷`_ øpwmpclkÙ§ãdefault8 pdisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþp÷`_ øpwmpclkÙ¨ãdefault8 pdisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþp ÷`_ øpwmpclkÙ©ãdefault8 pdisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþp0÷`_ øpwmpclkÙªãdefault8 pdisabledphy@fe830000,rockchip,rk3568-naneng-combphyóþƒ÷"} ørefapbpipe2"BõáDÇŽphy ¸« ʬ àpokay£phy@fe840000,rockchip,rk3568-naneng-combphyóþ„÷%~ ørefapbpipe2%BõáDÉŽphy ¸« Ê­ àpokay£phy@fe870000,rockchip,rk3568-csi-dphyóþ‡÷yøpclk àDºŽapbn  pdisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyóþ… ørefpclk÷z à% ŽapbD» pdisabled£Omipi-dphy@fe860000,rockchip,rk3568-dsi-dphyóþ† ørefpclk÷{ à% ŽapbD¼ pdisabled£Pusb2phy@fe8a0000,rockchip,rk3568-usb2phyóþŠ÷øphyclkÆclk_usbphy0_480m �‡ ë®pokay£host-port àpokay û¯£otg-port àpokay£usb2phy@fe8b0000,rockchip,rk3568-usb2phyóþ‹÷øphyclkÆclk_usbphy1_480m �ˆ ë°pokayhost-port àpokay û±£otg-port àpokay£pinctrl,rockchip,rk3568-pinctrln ¤X ñ£²gpio@fdd60000,rockchip,gpio-bankóýÖ �!÷.   ²  "k€£#gpio@fe740000,rockchip,gpio-bankóþt �"÷cd  ²  "k€gpio@fe750000,rockchip,gpio-bankóþu �#÷ef  ²@  "k€gpio@fe760000,rockchip,gpio-bankóþv �$÷gh  ²`  "k€£[gpio@fe770000,rockchip,gpio-bankóþw �%÷ij  ²€  "k€pcfg-pull-up .£µpcfg-pull-none ;£³pcfg-pull-none-drv-level-1 ; H£·pcfg-pull-none-drv-level-2 ; H£¶pcfg-pull-none-drv-level-3 ; H£ºpcfg-pull-up-drv-level-1 . H£¹pcfg-pull-up-drv-level-2 . H£´pcfg-pull-none-smt ; W£¸acodecaudiopwmbt656bt1120camcan0can0m0-pins l ³ ³£Ãcan1can1m0-pins l³³£Äcan2can2m0-pins l ³ ³£Åcifclk32kclk32k-out0 l³£cpuebcedpdpemmcemmc-bus8€ l ´ ´´´´´´´£bemmc-clk l´£cemmc-cmd l´£deth0eth1flashfspifspi-pins` l³³³³³³£agmac0gmac1gpuhdmitxhdmitxm0-cec l³£Shdmitx-scl l³£Qhdmitx-sda l³£Ri2c0i2c0-xfer l ¸ ¸£!i2c1i2c1-xfer l ¸ ¸£}i2c2i2c2m0-xfer l ¸¸£~i2c3i2c3m0-xfer l¸¸£i2c4i2c4m0-xfer l ¸ ¸£€i2c5i2c5m0-xfer l ¸ ¸£�i2s1i2s1m0-lrckrx l³£ii2s1m0-lrcktx l³£hi2s1m0-sclkrx l³£gi2s1m0-sclktx l³£fi2s1m0-sdi0 l ³£ji2s1m0-sdi1 l ³£ki2s1m0-sdi2 l ³£li2s1m0-sdi3 l³£mi2s1m0-sdo0 l³£ni2s1m0-sdo1 l³£oi2s1m0-sdo2 l ³£pi2s1m0-sdo3 l ³£qi2s2i2s2m0-lrcktx l³£si2s2m0-sclktx l³£ri2s2m0-sdi l³£ti2s2m0-sdo l³£ui2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk l³£vpdmm0-clk1 l³£wpdmm0-sdi0 l ³£xpdmm0-sdi1 l ³£ypdmm0-sdi2 l ³£zpdmm0-sdi3 l³£{pmicpmic-int lµ£$pmupwm0pwm0m0-pins l³£(pwm1pwm1m0-pins l³£)pwm2pwm2m0-pins l³£*pwm3pwm3-pins l³£+pwm4pwm4-pins l³£Ÿpwm5pwm5-pins l³£ pwm6pwm6-pins l³£¡pwm7pwm7-pins l³£¢pwm8pwm8m0-pins l ³££pwm9pwm9m0-pins l ³£¤pwm10pwm10m0-pins l ³£¥pwm11pwm11m0-pins l³£¦pwm12pwm12m0-pins l³£§pwm13pwm13m0-pins l³£¨pwm14pwm14m0-pins l³£©pwm15pwm15m0-pins l³£ªrefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ l´´´´£]sdmmc0-clk l´£^sdmmc0-cmd l´£_sdmmc0-det lµ£`sdmmc1sdmmc2spdifspdifm0-tx l³£|spi0spi0m0-pins0 l ³³³£…spi0m0-cs0 l³£ƒspi0m0-cs1 l³£„spi1spi1m0-pins0 l ³³³£ˆspi1m0-cs0 l³£†spi1m0-cs1 l³£‡spi2spi2m0-pins0 l³³³£‹spi2m0-cs0 l³£‰spi2m0-cs1 l³£Šspi3spi3m0-pins0 l ³³ ³£Žspi3m0-cs0 l³£Œspi3m0-cs1 l³£�tsadctsadc-shutorg l³£œtsadc-pin l³£�uart0uart0-xfer lµµ£'uart1uart1m0-xfer l µ µ£�uart2uart2m0-xfer lµµ£�uart3uart3m0-xfer lµµ£‘uart4uart4m0-xfer lµµ£’uart5uart5m0-xfer lµµ£“uart6uart6m0-xfer lµµ£”uart7uart7m0-xfer lµµ£•uart8uart8m0-xfer lµµ£–uart9uart9m0-xfer lµµ£—vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2hym8563hym8563-int lµ£‚usbvcc5v0-usb-host-en l³£Évcc5v0-usb-otg-en l³£Ëgpio-ledslan-led-pin l³£Ípower-led-pin l³£Îwan-led-pin l³£Ïwlan-led-pin l³£Ðpciepcie20-reset-pin lµ£Zrockchip-keyreset-button-pin lµ£Ìsata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcióü÷–—˜øsatapmaliverxoob �^  sata-phy% pdisabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconóýÇ£Æqos@fe190080,rockchip,rk3568-qossysconóþ€ £?qos@fe190100,rockchip,rk3568-qossysconóþ £@qos@fe190200,rockchip,rk3568-qossysconóþ £Asyscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconóýË€£»phy@fe8c0000,rockchip,rk3568-pcie3-phyóþŒ à÷&'wørefclk_mrefclk_npclkD¾Žphy z»pokay ‹£½pcie@fe270000,rockchip,rk3568-pcie ±(÷ˆ‰Š‹Œ$øaclk_mstaclk_slvaclk_dbipclkauxçpci<� Ÿž�œ^syspmcmsglegacyerr€»`μ¼¼¼Üíü "½  pcie-phy%0óÀ@@þ'òTñòòò ò à@@@YdbiapbconfigD±Žpipepokay ,# –¾legacy-interrupt-controllerk€ ��£¼pcie@fe280000,rockchip,rk3568-pcie ±(÷��‘’“$øaclk_mstaclk_slvaclk_dbipclkauxçpci<�¥¤£¢¡^syspmcmsglegacyerr€»`ο¿¿¿Üíü  "½  pcie-phy%0óÀ€@þ(ðTñððð ð à@€@YdbiapbconfigDÁŽpipepokay ,# –¾legacy-interrupt-controllerk€ �¢£¿ethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20aóþ*�^macirqeth_wake_irq@÷‚……¸´µ…¹Wøstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refD× Žstmmacethn ³ÀÃÔÁçÂú pdisabledmdio,snps,dwmac-mdio stmmac-axi-config £Àrx-queues-config-£Áqueue0tx-queues-configC£Âqueue0can@fe570000,rockchip,rk3568v2-canfdóþW �÷A@ øbaudpclkDUT ŽcoreapbãdefaultÙà pdisabledcan@fe580000,rockchip,rk3568v2-canfdóþX �÷CB øbaudpclkDWV ŽcoreapbãdefaultÙÄ pdisabledcan@fe590000,rockchip,rk3568v2-canfdóþY �÷ED øbaudpclkDYX ŽcoreapbãdefaultÙÅ pdisabledphy@fe820000,rockchip,rk3568-naneng-combphyóþ‚÷| ørefapbpipe2BõáDÅŽphy ¸« ÊÆ àpokay£chosen ¦serial2:1500000n8hdmi-con,hdmi-connectorîaportendpointcÇ£Wvdd-usbc-regulator,regulator-fixed ˜vdd_usbc§»ÍLK@åLK@£Èvcc3v3-sys-regulator,regulator-fixed ˜vcc3v3_sys§»Í2Z å2Z È£%vcc5v0-sys-regulator,regulator-fixed ˜vcc5v0_sys§»ÍLK@åLK@È£"vcc3v3-pcie-regulator,regulator-fixed ˜vcc3v3_pcieÍ2Z å2Z  ² 2# Å @"£¾vcc5v0-usb-regulator,regulator-fixed ˜vcc5v0_usb§»ÍLK@åLK@È£Êvcc5v0-usb-host-regulator,regulator-fixed ² Ö#ãdefaultÙɘvcc5v0_usb_host§»ÍLK@åLK@Ê£¯vcc5v0-usb-otg-regulator,regulator-fixed ² Ö#ãdefaultÙ˘vcc5v0_usb_otgÍLK@åLK@Ê£±pcie30-avdd0v9-regulator,regulator-fixed˜pcie30_avdd0v9§»Í » å » %pcie30-avdd1v8-regulator,regulator-fixed˜pcie30_avdd1v8§»Íw@åw@%gpio-keys ,gpio-keysãdefaultÙÌbutton-reset Û2 2# íreset ó˜gpio-leds ,gpio-ledsãdefaultÙÍÎÏÐled-lan þ lan 2[led-power þ power heartbeat 2[led-wan þ wan 2[led-wlan þ wlan 2[ interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosno-sdiono-mmcbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplynon-removabledma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplygpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfdata-lanesvpcie3v3-supplystdout-pathenable-active-highstartup-delay-usgpiodebounce-intervallabellinux,codecolorfunctionlinux,default-trigger