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–vddq_ddr_s0¥¹regulator-state-memdcdc-reg10 –vcc_1v8_s3¥¹Ëw@ãw@regulator-state-mem ä Èw@pldo-reg1 –avcc_1v8_s0¥¹Ëw@ãw@regulator-state-mempldo-reg2 –vcc_1v8_s0¥¹Ëw@ãw@regulator-state-mem Èw@pldo-reg3 –avdd_1v2_s0¥¹ËO€ãO€regulator-state-mempldo-reg4 –vcc_3v3_s0¥¹Ë2Z ã2Z û0Ôregulator-state-mempldo-reg5 –vccio_sd_s0¥¹Ëw@ã2Z û0Ôzregulator-state-mempldo-reg6 –pldo6_s3¥¹Ëw@ãw@regulator-state-mem ä Èw@nldo-reg1 –vdd_0v75_s3¥¹Ë q°ã q°regulator-state-mem ä È q°nldo-reg2–vdd_ddr_pll_s0¥¹Ë øPã øPregulator-state-mem È øPnldo-reg3 –avdd_0v75_s0¥¹Ë q°ã q°regulator-state-memnldo-reg4 –vdd_0v85_s0¥¹Ë øPã øPregulator-state-memnldo-reg5 –vdd_0v75_s0¥¹Ë q°ã q°regulator-state-memspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiþ³ÒI+š•spiclkapb_pclk4••9txrx˜ a²³´kdefault+ 1disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartþ´ÒL+«Ÿbaudclkapb_pclk4-- 9txrxaµkdefaultMC 1disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartþµÒM+¯ baudclkapb_pclk4- - 9txrxa¶kdefaultMC1okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartþ¶ÒN+³¡baudclkapb_pclk4- - 9txrxa·kdefaultMC 1disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartþ·ÒO+·¢baudclkapb_pclk4• • 9txrxa¸kdefaultMC 1disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartþ¸ÒP+»£baudclkapb_pclk4• • 9txrxa¹kdefaultMC 1disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartþ¹ÒQ+¿¤baudclkapb_pclk4• •9txrxaºkdefaultMC1okayserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartþºÒR+Ã¥baudclkapb_pclk4ll9txrxa»kdefaultMC1okayserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartþ»ÒS+Ǧbaudclkapb_pclk4l l 9txrxa¼kdefaultMC 1disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartþ¼ÒT+˧baudclkapb_pclk4l l 9txrxa½kdefaultMC 1disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½+LK pwmpclka¾kdefaultZ 1disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½+LK pwmpclka¿kdefaultZ 1disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½ +LK pwmpclkaÀkdefaultZ 1disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½0+LK pwmpclkaÁkdefaultZ 1disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾+ON pwmpclkaÂkdefaultZ 1disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾+ON pwmpclkaÃkdefaultZ 1disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾ +ON pwmpclkaÄkdefaultZ 1disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾0+ON pwmpclkaÅkdefaultZ 1disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿+RQ pwmpclkaÆkdefaultZ 1disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿+RQ pwmpclkaÇkdefaultZ 1disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿ +RQ pwmpclkaÈkdefaultZ 1disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿0+RQ pwmpclkaÉkdefaultZ 1disabledthermal-zonespackage-thermal ü  Êtripspackage-crit 0Á8 < criticalbigcore0-thermal üd  Êtripsbigcore0-alert 0L <ÐpassiveËbigcore0-crit 0Á8 < criticalcooling-mapsmap0 GË Lÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿbigcore2-thermal üd  Êtripsbigcore2-alert 0L <ÐpassiveÌbigcore2-crit 0Á8 < criticalcooling-mapsmap0 GÌ Lÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿlittlecore-thermal üd  Êtripslittlecore-alert 0L <ÐpassiveÍlittlecore-crit 0Á8 < criticalcooling-mapsmap0 GÍ0 Lÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcenter-thermal ü  Êtripscenter-crit 0Á8 < criticalgpu-thermal üd  Êtripsgpu-alert 0L <ÐpassiveÎgpu-crit 0Á8 < criticalcooling-mapsmap0 GÎ LÏÿÿÿÿÿÿÿÿnpu-thermal ü  Êtripsnpu-crit 0Á8 < criticaltsadc@fec00000rockchip,rk3588-tsadcþÀÒ�+ž�tsadcapb_pclk2žB„€XVW2tsadc-apbtsadc [ÔÀ r ‰aÐ ¤Ñkdefaultsleep ®1okayÊadc@fec10000rockchip,rk3588-saradcþÁÒŽ Ä+‘�saradcapb_pclkXU 2saradc-apb 1disabledi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2cþÈ+ˆ€ i2cpclkÒCaÒkdefault+1okayrtc@51haoyu,hym8563Q «Ò¸íhym8563kdefaultaÓ Öi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2cþÉ+‰� i2cpclkÒDaÔkdefault+ 1disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2cþÊ+Š‚ i2cpclkÒEaÕkdefault+ 1disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiþËÒJ+›–spiclkapb_pclk4l l9txrx˜ aÖרkdefault+ 1disabledefuse@fecc0000rockchip,rk3588-otpþÌ +Œ‹��otpapb_pclkphyarbX§¦¨ 2otpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c änpu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecellþÑ@ ÒZ[v+p apb_pclk�lphy@fed60000rockchip,rk3588-hdptx-phyþÖ + Trefapb>8X#cde!""2phyapbinitcmnlaneroplllcpllTÙ 1disabledphy@fed80000rockchip,rk3588-usbdp-phyþØ>+¡lVÚrefclkimmortalpclkutmi(X   2initcmnlanepcs_apbpma_apb éÛ üÜ Ý #Þ 1disabled#phy@fee00000rockchip,rk3588-naneng-combphyþà+¨vW refapbpipe2¨Bõá>X<C2phyapb 3+ Eß1okayqphy@fee20000rockchip,rk3588-naneng-combphyþâ+ªxW refapbpipe2ªBõá>X>E2phyapb 3+ Eà1okay(sram@ff001000 mmio-sramÿðÿð+pinctrlrockchip,rk3588-pinctrlTá+âgpio@fd8a0000rockchip,gpio-bankýŠÒ+qr ‚ [â V ’ò«gpio@fec20000rockchip,gpio-bankþÂÒ+st ‚ [â V ’ògpio@fec30000rockchip,gpio-bankþÃÒ+uv ‚ [â@ V ’ògpio@fec40000rockchip,gpio-bankþÄÒ+wx ‚ [â` V ’ògpio@fec50000rockchip,gpio-bankþÅÒ+yz ‚ [†V ’òðpcfg-pull-up gçpcfg-pull-down tåpcfg-pull-none ƒãpcfg-pull-none-drv-level-2 ƒ �épcfg-pull-up-drv-level-1 g �èpcfg-pull-up-drv-level-2 g �äpcfg-pull-none-smt ƒ Ÿæauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout ´ã|emmc-bus8€ ´ääääääää}emmc-clk ´ä~emmc-cmd ´äemmc-data-strobe ´å€eth1fspigmac1gpuhdmii2c0i2c0m2-xfer ´ææ,i2c1i2c1m0-xfer ´ æ æži2c2i2c2m0-xfer ´ æ æŸi2c3i2c3m0-xfer ´ æ æ i2c4i2c4m0-xfer ´ æ æ¡i2c5i2c5m0-xfer ´ æ æ¢i2c6i2c6m0-xfer ´ æ æÒi2c7i2c7m0-xfer ´ æ æÔi2c8i2c8m0-xfer ´ æ æÕi2s0i2s0-lrck ´ã�i2s0-sclk ´ã‚i2s0-sdi0 ´ãƒi2s0-sdi1 ´ã„i2s0-sdi2 ´ã…i2s0-sdi3 ´ã†i2s0-sdo0 ´ã‡i2s0-sdo1 ´ãˆi2s0-sdo2 ´ã‰i2s0-sdo3 ´ãŠi2s1i2s1m0-lrck ´ã‹i2s1m0-sclk ´ãŒi2s1m0-sdi0 ´ã�i2s1m0-sdi1 ´ãŽi2s1m0-sdi2 ´ã�i2s1m0-sdi3 ´ã�i2s1m0-sdo0 ´ ã‘i2s1m0-sdo1 ´ ã’i2s1m0-sdo2 ´ ã“i2s1m0-sdo3 ´ ã”i2s2i2s2m1-lrck ´ã–i2s2m1-sclk ´ ã—i2s2m1-sdi ´ ã˜i2s2m1-sdo ´ ã™i2s3i2s3-lrck ´ãši2s3-sclk ´ã›i2s3-sdi ´ãœi2s3-sdo ´ã�jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp ´çãããããã¬pmupwm0pwm0m0-pins ´ã/pwm1pwm1m0-pins ´ã0pwm2pwm2m1-pins ´ ã1pwm3pwm3m0-pins ´ã2pwm4pwm4m0-pins ´ ã¾pwm5pwm5m0-pins ´ ã¿pwm6pwm6m0-pins ´ ãÀpwm7pwm7m0-pins ´ ãÁpwm8pwm8m0-pins ´ ãÂpwm9pwm9m0-pins ´ ãÃpwm10pwm10m0-pins ´ ãÄpwm11pwm11m0-pins ´ ãÅpwm12pwm12m0-pins ´ ãÆpwm13pwm13m0-pins ´ ãÇpwm14pwm14m0-pins ´ ãÈpwm15pwm15m0-pins ´ ãÉrefclksatasata0sata1sata2sdiosdiom1-pins` ´ãççççç{sdmmcsdmmc-bus4@ ´ääääxsdmmc-clk ´äusdmmc-cmd ´ävsdmmc-det ´çwspdif0spdif1spi0spi0m0-pins0 ´èèè¥spi0m0-cs0 ´è£spi0m0-cs1 ´è¤spi1spi1m1-pins0 ´èèè¨spi1m1-cs0 ´è¦spi1m1-cs1 ´è§spi2spi2m2-pins0 ´è èèªspi2m2-cs0 ´ è©spi3spi3m1-pins0 ´è èè´spi3m1-cs0 ´è²spi3m1-cs1 ´è³spi4spi4m0-pins0 ´èèèØspi4m0-cs0 ´èÖspi4m0-cs1 ´è×tsadctsadc-shut-org ´ãÐuart0uart0m1-xfer ´ç ç.uart1uart1m1-xfer ´ ç çµuart2uart2m0-xfer ´ ç ç¶uart3uart3m1-xfer ´ ç ç·uart4uart4m1-xfer ´ ç ç¸uart5uart5m1-xfer ´ ç ç¹uart6uart6m0-xfer ´ ç çºuart7uart7m2-xfer ´ ç ç»uart8uart8m1-xfer ´ ç ç¼uart9uart9m1-xfer ´ ç ç½vopbt656gpio-functsadc-gpio-func ´ãÑeth0gmac0ledsled_user_en ´ãpcie2pcie2-0-rst ´ã÷pcie3pcie3x2-rst ´ãópcie3x2-vcc3v3-en ´ãpcie3x4-rst ´ãïpcie3x4-vcc3v3-en ´ãhym8563hym8563-int ´ãÓusbvcc5v0-host-en ´ãusb@fc400000rockchip,rk3588-dwc3snps,dwc3ü@@ÒÝ+—–•ref_clksuspend_clkbus_clk8otg @êëEusb2-phyusb3-phy Outmi_wide# XS_§Èé 1disabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsysconý[€syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsysconý\ÿsyscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsysconý\À@þsyscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfdý]@@+ýusb2phy@4000rockchip,rk3588-usb2phy@¸+ phyclk íusb480m_phy1ÒŠXn2phyapb 1disabledüotg-port> 1disabledêi2s@fddc8000rockchip,rk3588-i2s-tdmýÜ€Ò¼+ññîmclk_txmclk_rxhclk2ïÀ4l9tx# Xº2tx-m× 1disabledi2s@fddf4000rockchip,rk3588-i2s-tdmýß@Òº+99?mclk_txmclk_rxhclk26À4l9tx# XÚ2tx-m× 1disabledi2s@fddf8000rockchip,rk3588-i2s-tdmý߀Ò»+++'mclk_txmclk_rxhclk2(À4l9rx# XÇ2rx-m× 1disabledi2s@fde00000rockchip,rk3588-i2s-tdmýàÒ¾+&&"mclk_txmclk_rxhclk2#À4l9rx# Xî2rx-m× 1disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+è0+@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipeúpciPÒsyspmcmsglegacyerrò`ìììì$5DíL@î Epcie-phy# "Tððð ð à@ @0 @@þð‡dbiapbconfigX&+ 2pwrpipe1okaykdefaultaï Âð Îñlegacy-interrupt-controllerVò Òìpcie-ep@fe150000rockchip,rk3588-pcie-epP @ @þ @ @0‡dbidbi2apbaddr_spaceatu0+@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipe�Ò +syspmcmsglegacyerrdma0dma1dma2dma35L@î Epcie-phy# "X&+ 2pwrpipe 1disabledpcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+è0+AF<KPu)aclk_mstaclk_slvaclk_dbipclkauxpipeúpciPÒÿþsyspmcmsglegacyerrò`òòòò$5DíL@î Epcie-phy# "Tñññ ñ à@ @@0 @@@þñ‡dbiapbconfigX', 2pwrpipe1okaykdefaultaó Âð Îôlegacy-interrupt-controllerVò Òÿòpcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcieè /0+BG=LQ¯)aclk_mstaclk_slvaclk_dbipclkauxpipeúpciPÒóòñðïsyspmcmsglegacyerrò`õõõõ$5D o L@ö Epcie-phy# "Tòòò ò à@ €@0 @€@þò‡dbiapbconfigX(- 2pwrpipe+1okaykdefaulta÷ Âð Îølegacy-interrupt-controllerVò Òðõethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20aþ Òãâmacirqeth_wake_irq(+67X]40stmmacethclk_mac_refpclk_macaclk_macptp_ref# !X# 2stmmacethThk+|ùŒ�ú°ûà 1disabledmdiosnps,dwmac-mdio+stmmac-axi-configÌÖæùrx-queues-configöúqueue0queue1tx-queues-config ûqueue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahciþ"Ò(+c`fUpsatapmaliverxoobrefasic"+ 1disabledsata-port@04@@ö Esata-phyA P phy@fed90000rockchip,rk3588-usbdp-phyþÙ>+¡mWürefclkimmortalpclkutmi(X2initcmnlanepcs_apbpma_apb éý üÜ þ #Þ 1disabledëphy@fee10000rockchip,rk3588-naneng-combphyþá+©wW refapbpipe2©Bõá>X=D2phyapb 3+ Eÿ1okayöphy@fee80000rockchip,rk3588-pcie3-phyþè>+ypclkXH2phy 3+ Þ1okayîopp-table-cluster0operating-points-v2 ï opp-1200000000 úG†Œ  q° q°~ð œ@ opp-1296000000 úM?d  ÓX ÓX~ð œ@opp-table-cluster1operating-points-v2 ïopp-1200000000 úG†Œ  q° q°~ð œ@opp-1416000000 úTfr  ¢„ ¢„~ð œ@opp-1608000000 ú_Ø"  , ,~ð œ@opp-table-cluster2operating-points-v2 ïopp-1200000000 úG†Œ  q° q°~ð œ@opp-1416000000 úTfr  ¢„ ¢„~ð œ@opp-1608000000 ú_Ø"  , ,~ð œ@opp-tableoperating-points-v2!opp-300000000 úᣠ q° q° øPopp-400000000 úׄ  q° q° øPopp-500000000 úÍe  q° q° øPopp-600000000 ú#ÃF  q° q° øPopp-700000000 ú)¹'  q° q° øPgpio-leds gpio-ledsled-0 , £heartbeat È« 2heartbeatkdefaultavcc12v-dcin-regulatorregulator-fixed –vcc12v_dcin¥¹Ë·ã·vcc5v0-sys-regulatorregulator-fixed –vcc5v0_sys¥¹ËLK@ãLK@)vcc-1v1-nldo-s3-regulatorregulator-fixed–vcc_1v1_nldo_s3¥¹ËÈàãÈà)±chosen Hserial2:1500000n8vcc3v3-pcie2x1l0-regulatorregulator-fixed–vcc3v3_pcie2x1l0Ë2Z ã2Z  Tˆyøvcc3v3-pcie3x2-regulatorregulator-fixed e Èkdefaulta–vcc3v3_pcie3x2Ë2Z ã2Z  Tˆ)ôvcc3v3-pcie3x4-regulatorregulator-fixed e Èkdefaulta–vcc3v3_pcie3x4Ë2Z ã2Z  Tˆ)ñvcc5v0-host-regulatorregulator-fixed e xkdefaulta –vcc5v0_hostËLK@ãLK@¹¥)* compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesclock-namespower-domainsstatusdr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosiommusreg-namesrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpno-sdiono-mmcsd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellswakeup-sourcebitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsreset-gpiosvpcie3v3-supplyrockchip,phy-grfopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendcolorlinux,default-triggerstdout-pathstartup-delay-usenable-active-highgpio