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þrockchip,rk3588-dfi@×&0:äopcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?00CH>MR°)aclk_mstaclk_slvaclk_dbipclkauxpipeÿpciP×ø÷öõôsyspmcmsglegacyerr#4`GppppUfu0q0}Q* Vpcie-phy( "Tóóó ó à@ À@0 @À@þó¸dbiapbconfigi). cpwrpipe+6okay ‡r“sœdefault’tlegacy-interrupt-controller£# ×õppcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O00DI?NSs)aclk_mstaclk_slvaclk_dbipclkauxpipeÿpciP×ýüûúùsyspmcmsglegacyerr#4`GuuuuUfu@q@}Qv Vpcie-phy( "Tôôô ô à@ @0 A@þô¸dbiapbconfigi*/ cpwrpipe+6okay ‡r“wœdefault’xlegacy-interrupt-controller£# ×úuethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a þ ×êémacirqeth_wake_irq(067Y^50stmmacethclk_mac_refpclk_macaclk_macptp_ref( !i$ cstmmaceth…j¸,ÉyÙêzý{ 6disabledmdiosnps,dwmac-mdio+stmmac-axi-config#3yrx-queues-configCzqueue0queue1tx-queues-configY{queue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci þ!×(0b_eTosatapmaliverxoobrefasico+ 6disabledsata-port@0 �@Qv Vsata-phyŽ � sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci þ#×(0dagVqsatapmaliverxoobrefasico+ 6disabledsata-port@0 �@Q* Vsata-phyŽ � spi@fe2b0000 rockchip,sfc þ+@×Î0/0clk_sfchclk_sfc+6okayœdefault’|flash@0jedec,spi-nor ¬2ê¾Ïmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc þ,@×Ë 0  ­®biuciuciu-driveciu-sampleà° ëœdefault’}~€( (6okayÅëý �")1?‚Kƒmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc þ-@×Ì 0Š‹«¬biuciuciu-driveciu-sampleà° ëœdefault’„( % 6disabledmmc@fe2e0000rockchip,rk3588-dwcmshc þ.×Í7-., G ëÂn6 ëÂ(0,*+-.corebusaxiblocktimer° ëÂ’…†‡ˆ‰œdefault(iccorebusaxiblocktimer6okayÅ)X^l{i2s@fe470000rockchip,rk3588-i2s-tdm þG×´0+/(mclk_txmclk_rxhclk7)-ñe//jtxrx( &i*+ ctx-mrx-m•œdefault’Š‹Œ�Ž6okayportendpoint°i2s»,�ßi2s@fe480000rockchip,rk3588-i2s-tdm þH×µ0y}umclk_txmclk_rxhclke//jtxrxi^_ ctx-mrx-m•œdefault(’�‘’“”•–—˜™ 6disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2s þI×¶0i2s_clki2s_hclk7ñeššjtxrx( &œdefault’›œ�ž 6disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2s þJ×·0%i2s_clki2s_hclk7"ñeššjtxrx( &œdefault’Ÿ ¡¢ 6disabledinterrupt-controller@fe600000 arm,gic-v3  þ`þh× £Ãþaͨ8Ø#+msi-controller@fe640000arm,gic-v3-its þdØçqmsi-controller@fe660000arm,gic-v3-its þfØçúppi-partitionsinterrupt-partition-0òinterrupt-partition-1ò dma-controller@fea10000arm,pl330arm,primecell þ¡@ ×VWû0n apb_pclk /dma-controller@fea30000arm,pl330arm,primecell þ£@ ×XYû0o apb_pclk ši2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c þ©0ƒ{ i2cpclk×>’£œdefault+ 6disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c þª0„| i2cpclk×?’¤œdefault+6okayregulator@42rockchip,rk8602 Bª Çvdd_npu_s0Öêüdp~ð,üA.regulator-state-memLi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c þ«0…} i2cpclk×@’¥œdefault+ 6disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c þ¬0†~ i2cpclk×A’¦œdefault+ 6disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c þ­0‡ i2cpclk×B’§œdefault+ 6disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer þ® ×!0TW pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt þ¯0dc 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H. T. `. l. x. „. �. œ. ¨. µ´ Â. ϵ ܵ é. õ dvs1-null-pins gpio_pwrctrl1 pin_fun0±dvs2-null-pins gpio_pwrctrl2 pin_fun0²dvs3-null-pins gpio_pwrctrl3 pin_fun0³regulatorsdcdc-reg1êüdp~ð,0Ô Çvdd_gpu_s0 �"regulator-state-memLdcdc-reg2Öêüdp~ð,0ÔÇvdd_cpu_lit_s0regulator-state-memLdcdc-reg3Öêü L¸ q°,0Ô Çvdd_log_s0regulator-state-memL ; q°dcdc-reg4Öêüdp~ð,0Ô Çvdd_vdenc_s0regulator-state-memLdcdc-reg5Öêü L¸ » ,0Ô Çvdd_ddr_s0regulator-state-memL ; øPdcdc-reg6Öê Çvdd2_ddr_s3regulator-state-mem Wdcdc-reg7Öêü„€„€,0ÔÇvdd_2v0_pldo_s3´regulator-state-mem W ;„€dcdc-reg8Öêü2Z 2Z  Çvcc_3v3_s3regulator-state-mem W ;2Z dcdc-reg9Öê Çvddq_ddr_s0regulator-state-memLdcdc-reg10Öêüw@w@ Çvcc_1v8_s3regulator-state-mem W ;w@pldo-reg1Öêüw@w@ Çavcc_1v8_s0Öregulator-state-memLpldo-reg2Öêüw@w@ Çvcc_1v8_s0regulator-state-memL ;w@pldo-reg3ÖêüO€O€ Çavdd_1v2_s0regulator-state-memLpldo-reg4Öêü2Z 2Z ,0Ô Çvcc_3v3_s0regulator-state-memLpldo-reg5Öêüw@2Z ,0Ô Çvccio_sd_s0ƒregulator-state-memLpldo-reg6Öêüw@w@ Çpldo6_s3regulator-state-mem W ;w@nldo-reg1Öêü q° q° Çvdd_0v75_s3regulator-state-mem W ; q°nldo-reg2Öêü øP øPÇvdd_ddr_pll_s0regulator-state-memL ; øPnldo-reg3Öêü q° q° Çavdd_0v75_s0regulator-state-memLnldo-reg4Öêü øP øP Çvdd_0v85_s0regulator-state-memLnldo-reg5Öêü q° q° Çvdd_0v75_s0regulator-state-memLspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spi þ³×I0š•spiclkapb_pclkeššjtxrx  ’¶·¸œdefault+ 6disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uart þ´×L0«Ÿbaudclkapb_pclke// jtxrx’¹œdefault~t 6disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uart þµ×M0¯ baudclkapb_pclke/ / jtxrx’ºœdefault~t6okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uart þ¶×N0³¡baudclkapb_pclke/ / jtxrx’»œdefault~t 6disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uart þ·×O0·¢baudclkapb_pclkeš š jtxrx’¼œdefault~t 6disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uart þ¸×P0»£baudclkapb_pclkeš š jtxrx’½œdefault~t 6disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uart þ¹×Q0¿¤baudclkapb_pclkeš šjtxrx’¾œdefault~t 6disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uart þº×R0Ã¥baudclkapb_pclkennjtxrx’¿œdefault~t 6disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uart þ»×S0Ǧbaudclkapb_pclken n jtxrx’Àœdefault~t 6disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uart þ¼×T0˧baudclkapb_pclken n jtxrx’Áœdefault~t 6disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm þ½0LK pwmpclk’œdefault‹ 6disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm þ½0LK pwmpclk’Üdefault‹ 6disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm þ½ 0LK pwmpclk’Äœdefault‹ 6disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm þ½00LK pwmpclk’Åœdefault‹ 6disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¾0ON pwmpclk’Æœdefault‹ 6disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¾0ON pwmpclk’Çœdefault‹ 6disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¾ 0ON pwmpclk’Èœdefault‹ 6disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¾00ON pwmpclk’Éœdefault‹ 6disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¿0RQ pwmpclk’Êœdefault‹ 6disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¿0RQ pwmpclk’Ëœdefault‹ 6disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¿ 0RQ pwmpclk’Ìœdefault‹ 6disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm þ¿00RQ pwmpclk’Íœdefault‹ 6disabledthermal-zonespackage-thermal o … “Îtripspackage-crit £Á8 ¯ criticalbigcore0-thermal od … “Îtripsbigcore0-alert £L ¯ÐpassiveÏbigcore0-crit £Á8 ¯ criticalcooling-mapsmap0 ºÏ ¿ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿbigcore2-thermal od … “Îtripsbigcore2-alert £L ¯ÐpassiveÐbigcore2-crit £Á8 ¯ criticalcooling-mapsmap0 ºÐ ¿ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿlittlecore-thermal od … “Îtripslittlecore-alert £L ¯ÐpassiveÑlittlecore-crit £Á8 ¯ criticalcooling-mapsmap0 ºÑ0 ¿ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcenter-thermal o … “Îtripscenter-crit £Á8 ¯ criticalgpu-thermal od … “Îtripsgpu-alert £L ¯ÐpassiveÒgpu-crit £Á8 ¯ criticalcooling-mapsmap0 ºÒ ¿Óÿÿÿÿÿÿÿÿnpu-thermal o … “Îtripsnpu-crit £Á8 ¯ criticaltsadc@fec00000rockchip,rk3588-tsadc þÀ×�0ž�tsadcapb_pclk7žG„€iVWctsadc-apbtsadc ÎÔÀ å ü’Ô Õœdefaultsleep !6okayÎadc@fec10000rockchip,rk3588-saradc þÁ׎ 70‘�saradcapb_pclkiU csaradc-apb6okay IÖ i2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c þÈ0ˆ€ i2cpclk×C’לdefault+6okayâ @typec-portc@22 fcs,fusb302 " �×’Øœdefault UÙconnectorusb-c-connector adual kUSB-C qsource |�Èports+port@0 endpoint,Ú%port@1 endpoint,Ûêport@2 endpoint,Üërtc@51haoyu,hym8563 Q½òhym8563œdefault’Ý �× ˆi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c þÉ0‰� i2cpclk×D’Þœdefault+6okayâ @codec@1brealtek,rt5616 01mclk71G»€portendpoint,ß�i2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c þÊ0Š‚ i2cpclk×E’àœdefault+ 6disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spi þË×J0›–spiclkapb_pclken njtxrx  ’áâãœdefault+ 6disabledefuse@fecc0000rockchip,rk3588-otp þÌ 0Œ‹��otpapb_pclkphyarbi§¦¨ cotpapbarb+cpu-code@2 id@7 cpu-leakage@17 cpu-leakage@18 cpu-leakage@19 log-leakage@1a gpu-leakage@1b cpu-version@1c  –npu-leakage@28 (codec-leakage@29 )dma-controller@fed10000arm,pl330arm,primecell þÑ@ ×Z[û0p apb_pclk nphy@fed60000rockchip,rk3588-hdptx-phy þÖ 0 Trefapbo8i#cde!""cphyapbinitcmnlaneroplllcpll…ä 6disabledphy@fed80000rockchip,rk3588-usbdp-phy þØo0¡lVårefclkimmortalpclkutmi(i   cinitcmnlanepcs_apbpma_apb ›æ ®ç ¿è Õé6okay å ñ r r$port+endpoint@0 ,êÛendpoint@1 ,ëÜphy@fee00000rockchip,rk3588-naneng-combphy þà0¨vW refapbpipe7¨Gõáoi<Ccphyapb , 2ì6okayvphy@fee20000rockchip,rk3588-naneng-combphy þâ0ªxW refapbpipe7ªGõáoi>Ecphyapb , 2í6okay*sram@ff001000 mmio-sram ÿðÿð+pinctrlrockchip,rk3588-pinctrl…î+ïgpio@fd8a0000rockchip,gpio-bank ýŠ×0qr õ Hï £ #S THEADER_10HEADER_08HEADER_32IR receiver [PWM3_IR_M0]�gpio@fec20000rockchip,gpio-bank þÂ×0st õ Hï £ #ƒ THEADER_27HEADER_28HEADER_15HEADER_26HEADER_21HEADER_19HEADER_23HEADER_24HEADER_22HEADER_05HEADER_03gpio@fec30000rockchip,gpio-bank þÃ×0uv õ Hï@ £ #. TCSI1_11CSI1_12 gpio@fec40000rockchip,gpio-bank þÄ×0wx õ Hï` £ #Á THEADER_35HEADER_38HEADER_40HEADER_36HEADER_37DSI0_12HEADER_33DSI0_10HEADER_07HEADER_16HEADER_18HEADER_29HEADER_31HEADER_12DSI0_08DSI0_14HEADER_11HEADER_13DSI1_10gpio@fec50000rockchip,gpio-bank þÅ×0yz õ Hï€ £ #C TDSI1_08DSI1_14DSI1_12CSI0_11CSI0_12rpcfg-pull-up dôpcfg-pull-down qòpcfg-pull-none €ðpcfg-pull-none-drv-level-2 € �öpcfg-pull-up-drv-level-1 d �õpcfg-pull-up-drv-level-2 d �ñpcfg-pull-none-smt € œóauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout ±ð…emmc-bus8€ ±ññññññññ†emmc-clk ±ñ‡emmc-cmd ±ñˆemmc-data-strobe ±ò‰eth1fspifspim1-pins` ± ñ ññññ ñ|gmac1gpuhdmii2c0i2c0m2-xfer ±óó-i2c1i2c1m0-xfer ± ó ó£i2c2i2c2m0-xfer ± ó ó¤i2c3i2c3m0-xfer ± ó ó¥i2c4i2c4m0-xfer ± ó ó¦i2c5i2c5m0-xfer ± ó ó§i2c6i2c6m0-xfer ± ó ó×i2c7i2c7m0-xfer ± ó óÞi2c8i2c8m2-xfer ± ó óài2s0i2s0-lrck ±ðŠi2s0-mclk ±ð‹i2s0-sclk ±ðŒi2s0-sdi0 ±ð�i2s0-sdo0 ±ðŽi2s1i2s1m0-lrck ±ð�i2s1m0-sclk ±ð‘i2s1m0-sdi0 ±ð’i2s1m0-sdi1 ±ð“i2s1m0-sdi2 ±ð”i2s1m0-sdi3 ±ð•i2s1m0-sdo0 ± ð–i2s1m0-sdo1 ± ð—i2s1m0-sdo2 ± ð˜i2s1m0-sdo3 ± ð™i2s2i2s2m1-lrck ±ð›i2s2m1-sclk ± ðœi2s2m1-sdi ± ð�i2s2m1-sdo ± ðži2s3i2s3-lrck ±ðŸi2s3-sclk ±ð i2s3-sdi ±ð¡i2s3-sdo ±ð¢jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp ±ôðððððð°pmupwm0pwm0m0-pins ±ð1pwm1pwm1m1-pins ± ð2pwm2pwm2m0-pins ±ð3pwm3pwm3m0-pins ±ð4pwm4pwm4m0-pins ± ðÂpwm5pwm5m0-pins ± ðÃpwm6pwm6m0-pins ± ðÄpwm7pwm7m0-pins ± ðÅpwm8pwm8m0-pins ± ðÆpwm9pwm9m0-pins ± ðÇpwm10pwm10m0-pins ± ðÈpwm11pwm11m0-pins ± ðÉpwm12pwm12m0-pins ± ðÊpwm13pwm13m0-pins ± ðËpwm14pwm14m0-pins ± ðÌpwm15pwm15m0-pins ± ðÍrefclksatasata0sata1sata2sdiosdiom1-pins` ±ðôôôôô„sdmmcsdmmc-bus4@ ±ññññ€sdmmc-clk ±ñ}sdmmc-cmd ±ñ~sdmmc-det ±ôspdif0spdif1spi0spi0m0-pins0 ±õõõªspi0m0-cs0 ±õ¨spi0m0-cs1 ±õ©spi1spi1m1-pins0 ±õõõ­spi1m1-cs0 ±õ«spi1m1-cs1 ±õ¬spi2spi2m2-pins0 ±õ õõ¯spi2m2-cs0 ± õ®spi3spi3m1-pins0 ±õ õõ¸spi3m1-cs0 ±õ¶spi3m1-cs1 ±õ·spi4spi4m0-pins0 ±õõõãspi4m0-cs0 ±õáspi4m0-cs1 ±õâtsadctsadc-shut-org ±ðÔuart0uart0m1-xfer ±ô ô0uart1uart1m1-xfer ± ô ô¹uart2uart2m0-xfer ± ô ôºuart3uart3m1-xfer ± ô ô»uart4uart4m1-xfer ± ô ô¼uart5uart5m1-xfer ± ô ô½uart6uart6m1-xfer ± ô ô¾uart7uart7m1-xfer ± ô ô¿uart8uart8m1-xfer ± ô ôÀuart9uart9m1-xfer ± ô ôÁvopbt656gpio-functsadc-gpio-func ±ðÕeth0gmac0gpio-ledssys-led-pin ±ð usr-led-pin ±ð headphonehp-det ±ðhym8563hym8563-int ±ôÝir-receiverir-receiver-pin ±ð pciepcie2-0-rst ± ðpcie2-1-rst ±ðtpcie2-2-rst ±ðxpcie-m20-pwren ±ðpcie-m21-pwren ±ðusbtypec5v-pwren ±ðusbc0-int ±ôØ4g-lte-pwren ±ðusb@fc400000rockchip,rk3588-dwc3snps,dwc3 ü@@×Ý0—–•ref_clksuspend_clkbus_clkIotg Q÷øVusb2-phyusb3-phy `utmi_wide( iSp¸Ùú 6disabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon ý[€syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon ý\syscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsyscon ý\À@syscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd ý]@@+usb2phy@4000rockchip,rk3588-usb2phy @½0 phyclk òusb480m_phy1׊incphyapb 6disabledotg-porto 6disabled÷i2s@fddc8000rockchip,rk3588-i2s-tdm ýÜ€×¼0ññîmclk_txmclk_rxhclk7ïñenjtx( iºctx-m 6disabledi2s@fddf4000rockchip,rk3588-i2s-tdm ýß@׺099?mclk_txmclk_rxhclk76ñenjtx( iÚctx-m 6disabledi2s@fddf8000rockchip,rk3588-i2s-tdm ý߀×»0++'mclk_txmclk_rxhclk7(ñenjrx( iÇcrx-m 6disabledi2s@fde00000rockchip,rk3588-i2s-tdm ýà×¾0&&"mclk_txmclk_rxhclk7#ñenjrx( iîcrx-m 6disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+00@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipeÿpciP×syspmcmsglegacyerr#4`GùùùùUfuú}Qû Vpcie-phy( "Tððð ð à@ @0 @@þð¸dbiapbconfigi&+ cpwrpipe6okay ‡r“ülegacy-interrupt-controller£# ×ùpcie-ep@fe150000rockchip,rk3588-pcie-epP @ @þ @ @0¸dbidbi2apbaddr_spaceatu00@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipe�× +syspmcmsglegacyerrdma0dma1dma2dma3f}Qû Vpcie-phy( "i&+ cpwrpipe 6disabledpcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+00AF<KPu)aclk_mstaclk_slvaclk_dbipclkauxpipeÿpciP×ÿþsyspmcmsglegacyerr#4`GýýýýUfuú}Qû Vpcie-phy( "Tñññ ñ à@ @@0 @@@þñ¸dbiapbconfigi', cpwrpipe 6disabledlegacy-interrupt-controller£# ×ÿýpcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie /00BG=LQ¯)aclk_mstaclk_slvaclk_dbipclkauxpipeÿpciP×óòñðïsyspmcmsglegacyerr#4`GþþþþUfu q }Qÿ Vpcie-phy( "Tòòò ò à@ €@0 @€@þò¸dbiapbconfigi(- cpwrpipe+6okay ‡r “wœdefault’legacy-interrupt-controller£# ×ðþethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20a þ ×ãâmacirqeth_wake_irq(067X]40stmmacethclk_mac_refpclk_macaclk_macptp_ref( !i# cstmmaceth…j¸,ÉÙêý 6disabledmdiosnps,dwmac-mdio+stmmac-axi-config#3rx-queues-configCqueue0queue1tx-queues-configYqueue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci þ"×(0c`fUpsatapmaliverxoobrefasico+ 6disabledsata-port@0 �@Qÿ Vsata-phyŽ � phy@fed90000rockchip,rk3588-usbdp-phy þÙo0¡mWrefclkimmortalpclkutmi(icinitcmnlanepcs_apbpma_apb › ®ç ¿ Õé 6disabledøphy@fee10000rockchip,rk3588-naneng-combphy þá0©wW refapbpipe7©Gõáoi=Dcphyapb , 26okayÿphy@fee80000rockchip,rk3588-pcie3-phy þèo0ypclkiHcphy , ¿6okayûopp-table-cluster0operating-points-v2 Ð opp-1008000000 Û<Ü â L¸ L¸~ð ðœ@opp-1200000000 ÛG†Œ â ß4 ß4~ð ðœ@opp-1416000000 ÛTfr â ¢„ ¢„~ð ðœ@ opp-1608000000 Û_Ø" â øP øP~ð ðœ@opp-1800000000 ÛkIÒ â~ð~ð~ð ðœ@opp-table-cluster1operating-points-v2 Ðopp-1200000000 ÛG†Œ â L¸ L¸B@ ðœ@opp-1416000000 ÛTfr â  B@ ðœ@opp-1608000000 Û_Ø" â ¢„ ¢„B@ ðœ@opp-1800000000 ÛkIÒ â øP øPB@ ðœ@opp-2016000000 Ûx)¸ âHHB@ ðœ@opp-2208000000 Ûƒ›h âllB@ ðœ@opp-2400000000 Û�  âB@B@B@ ðœ@opp-table-cluster2operating-points-v2 Ðopp-1200000000 ÛG†Œ â L¸ L¸B@ ðœ@opp-1416000000 ÛTfr â  B@ ðœ@opp-1608000000 Û_Ø" â ¢„ ¢„B@ ðœ@opp-1800000000 ÛkIÒ â øP øPB@ ðœ@opp-2016000000 Ûx)¸ âHHB@ ðœ@opp-2208000000 Ûƒ›h âllB@ ðœ@opp-2400000000 Û�  âB@B@B@ ðœ@opp-tableoperating-points-v2!opp-300000000 Ûᣠâ L¸ L¸ øPopp-400000000 Ûׄ â L¸ L¸ øPopp-500000000 ÛÍe â L¸ L¸ øPopp-600000000 Û#ÃF â L¸ L¸ øPopp-700000000 Û)¹' â ®` ®` øPopp-800000000 Û/¯ â q° q° øPopp-900000000 Û5¤é â 5 5 øPopp-1000000000 Û;šÊ â øP øP øPadc-keys-0 adc-keys   buttons *w@ Ddbutton-maskrom kMask Rom R� ]Ðchosen wserial2:1500000n8ir-receivergpio-ir-receiver ��œdefault’ leds gpio-ledsled-0 �  ksystem-led ƒheartbeatœdefault’ led-1 �  kuser-ledœdefault’ soundsimple-audio-cardœdefault’ ™realtek,rt5616-codec °i2s É ã0HeadphoneHeadphonesMicrophoneMicrophone JackNHeadphonesHPOLHeadphonesHPORMIC1Microphone JackMicrophone Jackmicbias1simple-audio-card,cpu5simple-audio-card,codec5vcc12v-dcin-regulatorregulator-fixed Çvcc12v_dcinÖêü··vcc5v0-sys-regulatorregulator-fixed Çvcc5v0_sysÖêüLK@LK@Avcc4v0-sys-regulatorregulator-fixed Çvcc4v0_sysÖêü= = A.vcc-1v1-nldo-s3-regulatorregulator-fixedÇvcc-1v1-nldo-s3ÖêüÈàÈàA.µvcc3v3-pcie20-regulatorregulator-fixedÇvcc_3v3_pcie20Öêü2Z 2Z Awvbus5v0-typec-regulatorregulator-fixed? üœdefault’ÖêÇvbus5v0_typecüLK@LK@AÙvcc3v3-pcie2x1l0-regulatorregulator-fixed? ürœdefault’Çvcc3v3_pcie2x1l0ü2Z 2Z Asvcc3v3-pcie30-regulatorregulator-fixed? � œdefault’Çvcc3v3_pcie30ü2Z 2Z Aüvcc3v3-sd-s0-regulatorregulator-fixed ürê2Z ü2Z  Çvcc3v3_sd_s0A‚vdd-4g-3v3-regulatorregulator-fixed? ürœdefault’ Çvdd_4g_3v3ü2Z 2Z A+ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0mmc1cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesclock-namespower-domainsstatusmali-supplydr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirkusb-role-switchremote-endpointsnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosiommusreg-namesrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplyinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthfifo-depthcap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpno-mmcno-sdiosd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlydai-formatmclk-fsmbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-cssystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplyvbus-supplydata-rolelabelpower-rolesource-pdoswakeup-sourcebitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfmode-switchorientation-switchsbu1-dc-gpiossbu2-dc-gpiosrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesgpio-line-namesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallinux,codepress-threshold-microvoltstdout-pathlinux,default-triggersimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,hp-det-gpiosimple-audio-card,widgetssimple-audio-card,routingsound-daienable-active-high