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–vddq_ddr_s0¥¹regulator-state-memdcdc-reg10 –vcc_1v8_s3¥¹Ëw@ãw@regulator-state-mem – zw@pldo-reg1 –avcc_1v8_s0¥¹Ëw@ãw@regulator-state-mempldo-reg2 –vcc_1v8_s0¥¹Ëw@ãw@Ñregulator-state-mem zw@pldo-reg3 –avdd_1v2_s0¥¹ËO€ãO€regulator-state-mempldo-reg4 –vcc_3v3_s0¥¹Ë2Z ã2Z regulator-state-mempldo-reg5 –vccio_sd_s0¥¹Ëw@ã2Z regulator-state-mempldo-reg6 –pldo6_s3¥¹Ëw@ãw@regulator-state-mem – zw@nldo-reg1 –vdd_0v75_s3¥¹Ë q°ã q°regulator-state-mem – z q°nldo-reg2–vdd_ddr_pll_s0¥¹Ë øPã øPregulator-state-mem z øPnldo-reg3 –avdd_0v75_s0¥¹Ë Ç|ã Ç|regulator-state-memnldo-reg4 –vdd_0v85_s0¥¹Ë øPã øPregulator-state-memnldo-reg5 –vdd_0v75_s0¥¹Ë q°ã q°regulator-state-memspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiþ³ÒI+š•spiclkapb_pclk4““9txrxJ a±²³kdefault+ 1disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartþ´ÒL+«Ÿbaudclkapb_pclk4-- 9txrxa´kdefaultMC 1disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartþµÒM+¯ baudclkapb_pclk4- - 9txrxaµkdefaultMC1okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartþ¶ÒN+³¡baudclkapb_pclk4- - 9txrxa¶kdefaultMC 1disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartþ·ÒO+·¢baudclkapb_pclk4“ “ 9txrxa·kdefaultMC 1disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartþ¸ÒP+»£baudclkapb_pclk4“ “ 9txrxa¸kdefaultMC 1disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartþ¹ÒQ+¿¤baudclkapb_pclk4“ “9txrxa¹kdefaultMC 1disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartþºÒR+Ã¥baudclkapb_pclk4ll9txrxaºkdefaultMC 1disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartþ»ÒS+Ǧbaudclkapb_pclk4l l 9txrxa»kdefaultMC 1disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartþ¼ÒT+˧baudclkapb_pclk4l l 9txrxa¼kdefaultMC 1disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½+LK pwmpclka½kdefaultZ 1disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½+LK pwmpclka¾kdefaultZ 1disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½ +LK pwmpclka¿kdefaultZ 1disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½0+LK pwmpclkaÀkdefaultZ 1disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾+ON pwmpclkaÁkdefaultZ 1disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾+ON pwmpclkaÂkdefaultZ 1disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾ +ON pwmpclkaÃkdefaultZ 1disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾0+ON pwmpclkaÄkdefaultZ 1disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿+RQ pwmpclkaÅkdefaultZ 1disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿+RQ pwmpclkaÆkdefaultZ 1disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿ +RQ pwmpclkaÇkdefaultZ 1disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿0+RQ pwmpclkaÈkdefaultZ 1disabledthermal-zonespackage-thermal ® Ä ÒÉtripspackage-crit âÁ8 î criticalbigcore0-thermal ®d Ä ÒÉtripsbigcore0-alert âL îÐpassiveÊbigcore0-crit âÁ8 î criticalcooling-mapsmap0 ùÊ þÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿbigcore2-thermal ®d Ä ÒÉtripsbigcore2-alert âL îÐpassiveËbigcore2-crit âÁ8 î criticalcooling-mapsmap0 ùË þÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿlittlecore-thermal ®d Ä ÒÉtripslittlecore-alert âL îÐpassiveÌlittlecore-crit âÁ8 î criticalcooling-mapsmap0 ùÌ0 þÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcenter-thermal ® Ä ÒÉtripscenter-crit âÁ8 î criticalgpu-thermal ®d Ä ÒÉtripsgpu-alert âL îÐpassiveÍgpu-crit âÁ8 î criticalcooling-mapsmap0 ùÍ þÎÿÿÿÿÿÿÿÿnpu-thermal ® Ä ÒÉtripsnpu-crit âÁ8 î criticaltsadc@fec00000rockchip,rk3588-tsadcþÀÒ�+ž�tsadcapb_pclk2žB„€XVW2tsadc-apbtsadc ÔÀ $ ;aÏ VÐkdefaultsleep `1okayÉadc@fec10000rockchip,rk3588-saradcþÁÒŽ v+‘�saradcapb_pclkXU 2saradc-apb1okay ˆÑi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2cþÈ+ˆ€ i2cpclkÒCaÒkdefault+ 1disabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2cþÉ+‰� i2cpclkÒDaÓkdefault+ 1disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2cþÊ+Š‚ i2cpclkÒEaÔkdefault+ 1disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiþËÒJ+›–spiclkapb_pclk4l l9txrxJ aÕÖ×kdefault+ 1disabledefuse@fecc0000rockchip,rk3588-otpþÌ +Œ‹��otpapb_pclkphyarbX§¦¨ 2otpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c ”npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecellþÑ@ ÒZ[+p apb_pclk1lphy@fed60000rockchip,rk3588-hdptx-phyþÖ + Trefapb>8X#cde!""2phyapbinitcmnlaneroplllcpllTØ 1disabledphy@fed80000rockchip,rk3588-usbdp-phyþØ>+¡lVÙrefclkimmortalpclkutmi(X   2initcmnlanepcs_apbpma_apb ™Ú ¬Û ½Ü ÓÝ 1disabled#phy@fee00000rockchip,rk3588-naneng-combphyþà+¨vW refapbpipe2¨Bõá>X<C2phyapb ã* õÞ1okayqphy@fee20000rockchip,rk3588-naneng-combphyþâ+ªxW refapbpipe2ªBõá>X>E2phyapb ã* õß1okay(sram@ff001000 mmio-sramÿðÿð+pinctrlrockchip,rk3588-pinctrlTà+ágpio@fd8a0000rockchip,gpio-bankýŠÒ+qrQ á Vaòžgpio@fec20000rockchip,gpio-bankþÂÒ+stQ á Vaògpio@fec30000rockchip,gpio-bankþÃÒ+uvQ á@ Vaògpio@fec40000rockchip,gpio-bankþÄÒ+wxQ á` Vaògpio@fec50000rockchip,gpio-bankþÅÒ+yzQ ဠVaòûpcfg-pull-up æpcfg-pull-down $äpcfg-pull-none 3âpcfg-pull-none-drv-level-2 3 @èpcfg-pull-up-drv-level-1  @çpcfg-pull-up-drv-level-2  @ãpcfg-pull-none-smt 3 Oåauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout dâzemmc-bus8€ dãããããããã{emmc-clk dã|emmc-cmd dã}emmc-data-strobe dä~eth1fspigmac1gpuhdmii2c0i2c0m2-xfer dåå+i2c1i2c1m0-xfer d å åœi2c2i2c2m0-xfer d å å�i2c3i2c3m0-xfer d å å i2c4i2c4m0-xfer d å å¡i2c5i2c5m0-xfer d å å¢i2c6i2c6m0-xfer d å åÒi2c7i2c7m0-xfer d å åÓi2c8i2c8m0-xfer d å åÔi2s0i2s0-lrck dâi2s0-sclk dâ€i2s0-sdi0 dâ�i2s0-sdi1 dâ‚i2s0-sdi2 dâƒi2s0-sdi3 dâ„i2s0-sdo0 dâ…i2s0-sdo1 dâ†i2s0-sdo2 dâ‡i2s0-sdo3 dâˆi2s1i2s1m0-lrck dâ‰i2s1m0-sclk dâŠi2s1m0-sdi0 dâ‹i2s1m0-sdi1 dâŒi2s1m0-sdi2 dâ�i2s1m0-sdi3 dâŽi2s1m0-sdo0 d â�i2s1m0-sdo1 d â�i2s1m0-sdo2 d â‘i2s1m0-sdo3 d â’i2s2i2s2m1-lrck dâ”i2s2m1-sclk d â•i2s2m1-sdi d â–i2s2m1-sdo d â—i2s3i2s3-lrck dâ˜i2s3-sclk dâ™i2s3-sdi dâši2s3-sdo dâ›jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp dæââââââ«pmupwm0pwm0m0-pins dâ/pwm1pwm1m0-pins dâ0pwm2pwm2m0-pins dâ1pwm3pwm3m0-pins dâ2pwm4pwm4m0-pins d â½pwm5pwm5m0-pins d â¾pwm6pwm6m0-pins d â¿pwm7pwm7m0-pins d âÀpwm8pwm8m0-pins d âÁpwm9pwm9m0-pins d âÂpwm10pwm10m0-pins d âÃpwm11pwm11m0-pins d âÄpwm12pwm12m0-pins d âÅpwm13pwm13m0-pins d âÆpwm14pwm14m0-pins d âÇpwm15pwm15m0-pins d âÈrefclksatasata0sata1sata2sdiosdiom1-pins` dâæææææysdmmcsdmmc-bus4@ dããããxsdmmc-clk dãusdmmc-cmd dãvsdmmc-det dæwspdif0spdif1spi0spi0m0-pins0 dççç¥spi0m0-cs0 dç£spi0m0-cs1 dç¤spi1spi1m1-pins0 dççç¨spi1m1-cs0 dç¦spi1m1-cs1 dç§spi2spi2m2-pins0 dç ççªspi2m2-cs0 d ç©spi3spi3m1-pins0 dç çç³spi3m1-cs0 dç±spi3m1-cs1 dç²spi4spi4m0-pins0 dççç×spi4m0-cs0 dçÕspi4m0-cs1 dçÖtsadctsadc-shut-org dâÏuart0uart0m1-xfer dæ æ.uart1uart1m1-xfer d æ æ´uart2uart2m0-xfer d æ æµuart3uart3m1-xfer d æ æ¶uart4uart4m1-xfer d æ æ·uart5uart5m1-xfer d æ æ¸uart6uart6m1-xfer d æ æ¹uart7uart7m1-xfer d æ æºuart8uart8m1-xfer d æ æ»uart9uart9m1-xfer d æ æ¼vopbt656gpio-functsadc-gpio-func dâÐeth0gmac0gmac0-miim dââõgmac0-rx-bus20 dâââ÷gmac0-tx-bus20 dâââögmac0-rgmii-clk dâ âøgmac0-rgmii-bus@ dââ â âùrtl8211frtl8211f-rst d âúhym8563hym8563-int dæŸusbvcc5v0-host-en dâusb@fc400000rockchip,rk3588-dwc3snps,dwc3ü@@ÒÝ+—–•ref_clksuspend_clkbus_clk8otg @éêEusb2-phyusb3-phy Outmi_wide# XS_§Èé 1disabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsysconý[€syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsysconý\ÿsyscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsysconý\À@þsyscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfdý]@@+ýusb2phy@4000rockchip,rk3588-usb2phy@¸+ phyclk íusb480m_phy1ÒŠXn2phyapb 1disabledüotg-port> 1disabledéi2s@fddc8000rockchip,rk3588-i2s-tdmýÜ€Ò¼+ññîmclk_txmclk_rxhclk2ïÀ4l9tx# Xº2tx-m× 1disabledi2s@fddf4000rockchip,rk3588-i2s-tdmýß@Òº+99?mclk_txmclk_rxhclk26À4l9tx# XÚ2tx-m× 1disabledi2s@fddf8000rockchip,rk3588-i2s-tdmý߀Ò»+++'mclk_txmclk_rxhclk2(À4l9rx# XÇ2rx-m× 1disabledi2s@fde00000rockchip,rk3588-i2s-tdmýàÒ¾+&&"mclk_txmclk_rxhclk2#À4l9rx# Xî2rx-m× 1disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+è0+@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipeúpciPÒsyspmcmsglegacyerrò`ëëëë$5DìL@í Epcie-phy# "Tððð ð à@ @0 @@þð‡dbiapbconfigX&+ 2pwrpipe 1disabledlegacy-interrupt-controllerVò Òëpcie-ep@fe150000rockchip,rk3588-pcie-epP @ @þ @ @0‡dbidbi2apbaddr_spaceatu0+@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipe�Ò +syspmcmsglegacyerrdma0dma1dma2dma35L@í Epcie-phy# "X&+ 2pwrpipe 1disabledpcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+è0+AF<KPu)aclk_mstaclk_slvaclk_dbipclkauxpipeúpciPÒÿþsyspmcmsglegacyerrò`îîîî$5DìL@í Epcie-phy# "Tñññ ñ à@ @@0 @@@þñ‡dbiapbconfigX', 2pwrpipe 1disabledlegacy-interrupt-controllerVò Òÿîpcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcieè /0+BG=LQ¯)aclk_mstaclk_slvaclk_dbipclkauxpipeúpciPÒóòñðïsyspmcmsglegacyerrò`ïïïï$5D o L@ð Epcie-phy# "Tòòò ò à@ €@0 @€@þò‡dbiapbconfigX(- 2pwrpipe+ 1disabledlegacy-interrupt-controllerVò Òðïethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20aþ Òãâmacirqeth_wake_irq(+67X]40stmmacethclk_mac_refpclk_macaclk_macptp_ref# !X# 2stmmacethThk*|ñŒ�ò°óÃ1okay routput ô Šrgmii-rxidaõö÷øùkdefault “ œCmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c916kdefaultaú ¥N  µ†  Çû ôstmmac-axi-configÌÖæñrx-queues-configöòqueue0queue1tx-queues-config óqueue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahciþ"Ò(+c`fUpsatapmaliverxoobrefasic"+ 1disabledsata-port@04@@ð Esata-phyA P phy@fed90000rockchip,rk3588-usbdp-phyþÙ>+¡mWürefclkimmortalpclkutmi(X2initcmnlanepcs_apbpma_apb ™ý ¬Û ½þ ÓÝ 1disabledêphy@fee10000rockchip,rk3588-naneng-combphyþá+©wW refapbpipe2©Bõá>X=D2phyapb ã* õÿ 1disabledðphy@fee80000rockchip,rk3588-pcie3-phyþè>+ypclkXH2phy ã* Ó 1disabledíopp-table-cluster0operating-points-v2 ä opp-1008000000 ï<Ü ö L¸ L¸~ð œ@opp-1200000000 ïG†Œ ö ß4 ß4~ð œ@opp-1416000000 ïTfr ö ¢„ ¢„~ð œ@ opp-1608000000 ï_Ø" ö øP øP~ð œ@opp-1800000000 ïkIÒ ö~ð~ð~ð œ@opp-table-cluster1operating-points-v2 äopp-1200000000 ïG†Œ ö L¸ L¸B@ œ@opp-1416000000 ïTfr ö  B@ œ@opp-1608000000 ï_Ø" ö ¢„ ¢„B@ œ@opp-1800000000 ïkIÒ ö øP øPB@ œ@opp-2016000000 ïx)¸ öHHB@ œ@opp-2208000000 h öllB@ œ@opp-2400000000 ï�  öB@B@B@ œ@opp-table-cluster2operating-points-v2 äopp-1200000000 ïG†Œ ö L¸ L¸B@ œ@opp-1416000000 ïTfr ö  B@ œ@opp-1608000000 ï_Ø" ö ¢„ ¢„B@ œ@opp-1800000000 ïkIÒ ö øP øPB@ œ@opp-2016000000 ïx)¸ öHHB@ œ@opp-2208000000 h öllB@ œ@opp-2400000000 ï�  öB@B@B@ œ@opp-tableoperating-points-v2!opp-300000000 ïᣠö L¸ L¸ øPopp-400000000 ïׄ ö L¸ L¸ øPopp-500000000 ïÍe ö L¸ L¸ øPopp-600000000 ï#ÃF ö L¸ L¸ øPopp-700000000 ï)¹' ö ®` ®` øPopp-800000000 ï/¯ ö q° q° øPopp-900000000 ï5¤é ö 5 5 øPopp-1000000000 ï;šÊ ö øP øP øPchosen !serial2:1500000n8adc-keys adc-keys - 9buttons Jw@ ddbutton-vol-up rVolume Up xs ƒBhbutton-vol-down rVolume Down xr ƒ\èbutton-menu rMenu x‹ ƒ ”�button-escape rEscape x ƒØ8backlightpwm-backlight � ªa¨pcie20-avdd0v85-regulatorregulator-fixed–pcie20_avdd0v85¥¹Ë øPã øPpcie20-avdd1v8-regulatorregulator-fixed–pcie20_avdd1v8¥¹Ëw@ãw@pcie30-avdd0v75-regulatorregulator-fixed–pcie30_avdd0v75¥¹Ë q°ã q°pcie30-avdd1v8-regulatorregulator-fixed–pcie30_avdd1v8¥¹Ëw@ãw@vcc12v-dcin-regulatorregulator-fixed –vcc12v_dcin¥¹Ë·ã·vcc5v0-host-regulatorregulator-fixed ¯ Âûkdefaulta –vcc5v0_host¹¥ËLK@ãLK@)vcc5v0-sys-regulatorregulator-fixed –vcc5v0_sys¥¹ËLK@ãLK@,vcc5v0-usbdcin-regulatorregulator-fixed–vcc5v0_usbdcin¥¹ËLK@ãLK@ vcc5v0-usb-regulatorregulator-fixed –vcc5v0_usb¥¹ËLK@ãLK@ vcc-1v1-nldo-s3-regulatorregulator-fixed–vcc_1v1_nldo_s3¥¹ËÈàãÈà,° compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesclock-namespower-domainsstatusdr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosiommusreg-namesrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthmmc-hs400-1_8vmmc-hs400-enhanced-strobeno-sdiono-sdnon-removablerockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellswakeup-sourcenum-csgpio-controller#gpio-cellsspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplypinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplybitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsclock_in_outphy-handlephy-moderx_delaytx_delayreset-assert-usreset-deassert-usreset-gpiosrockchip,phy-grfopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltpower-supplypwmsenable-active-highgpio