Ð þíGÇ8;T( s;turing,rk1rockchip,rk3588 +7Turing Machines RK1aliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000ƒ/i2c@feca0000ˆ/serial@fd890000�/serial@feb40000˜/serial@feb50000 /serial@feb60000¨/serial@feb70000°/serial@feb80000¸/serial@feb90000À/serial@feba0000È/serial@febb0000Ð/serial@febc0000Ø/spi@feb00000Ý/spi@feb10000â/spi@feb20000ç/spi@feb30000ì/spi@fecb0000ñ/ethernet@fe1c0000û/mmc@fe2e0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cluster2core0core1 cpu@0cpuarm,cortex-a55psci"5 < L0£,a q€~@�€�€ª@¼€É Úäô "cpu@100cpuarm,cortex-a55psci"5 a q€~@�€�€ª@¼€ÉÚäô "cpu@200cpuarm,cortex-a55psci"5 a q€~@�€�€ª@¼€ÉÚäô "cpu@300cpuarm,cortex-a55psci"5 a q€~@�€�€ª@¼€ÉÚäô "cpu@400cpuarm,cortex-a76psci"5 < L0£,a q~@��ª@¼ÉÚ ô"cpu@500cpuarm,cortex-a76psci"5 a q~@��ª@¼ÉÚ ô"cpu@600cpuarm,cortex-a76psci"5 < L0£,a q~@��ª@¼ÉÚ ô"cpu@700cpuarm,cortex-a76psci"5 a q~@��ª@¼ÉÚ ô" idle-states*pscicpu-sleeparm,idle-state7H_dpx€è" l2-cache-l0caches€@’‘�É" l2-cache-l1caches€@’‘�É"l2-cache-l2caches€@’‘�É"l2-cache-l3caches€@’‘�É"l2-cache-b0caches€@’‘�É"l2-cache-b1caches€@’‘�É"l2-cache-b2caches€@’‘�É"l2-cache-b3caches€@’‘�É"l3-cachecaches0€@’‘�"display-subsystemrockchip,display-subsystem«firmwareopteelinaro,optee-tzsmcscmi arm,scmi-smc±‚¼+protocol@14Â" protocol@16Ïpmu-a55arm,cortex-a55-pmuÜpmu-a76arm,cortex-a76-pmuÜpsci arm,psci-1.0smcclock-0 fixed-clockç)׫€÷spllÂtimerarm,armv8-timerPÜ    % sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockçn6÷xin24mÂclock-2 fixed-clockç€÷xin32kÂsram@10f000 mmio-sramðð+sram@0arm,scmi-shmem"gpu@fb000000*rockchip,rk3588-maliarm,mali-valhall-csfû ô< L ëÂ5!corecoregroupstacksÚ ¦0Ü\]^  jobmmugpu-  ;disabled!"Öusb@fc000000rockchip,rk3588-dwc3snps,dwc3ü@ÜÜ5”“’!ref_clksuspend_clkbus_clkBotg J"#Ousb2-phyusb3-phy Yutmi_wide- bRi�™±Òó ;disabledusb@fc800000"rockchip,rk3588-ehcigeneric-ehciü€Ü×5Ž�À$J%Ousb-  ;disabledusb@fc840000"rockchip,rk3588-ohcigeneric-ohciü„ÜØ5Ž�À$J%Ousb-  ;disabledusb@fc880000"rockchip,rk3588-ehcigeneric-ehciüˆÜÚ5�‘À&J'Ousb-  ;disabledusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohciüŒÜÛ5�‘À&J'Ousb-  ;disabledusb@fcd00000rockchip,rk3588-dwc3snps,dwc3üÐ@ÜÞ(5jihkr&!ref_clksuspend_clkbus_clkutmipipeBhostJ( Ousb3-phy Yutmi_wideb4i±Òó ;disablediommu@fc900000 arm,smmu-v3ü� @Üqsvo eventqgerrorpriqcmdq-sync/ ;disablediommu@fcb00000 arm,smmu-v3ü° @Ü}‚{ eventqgerrorpriqcmdq-sync/ ;disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdýX "lsyscon@fd58c000rockchip,rk3588-sys-grfsysconýXÀ"gsyscon@fd5a4000rockchip,rk3588-vop-grfsysconýZ@ "hsyscon@fd5a6000rockchip,rk3588-vo0-grfsysconýZ` 5é"åsyscon@fd5a8000rockchip,rk3588-vo1-grfsysconýZ€@5Ñ"isyscon@fd5ac000rockchip,rk3588-usb-grfsysconýZÀ@"ãsyscon@fd5b0000rockchip,rk3588-php-grfsysconý[")syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsysconý[À"æsyscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsysconý\@"çsyscon@fd5c8000$rockchip,rk3588-usbdpphy-grfsysconý\€@"äsyscon@fd5d0000.rockchip,rk3588-usb2phy-grfsysconsimple-mfdý]@+"âusb2phy@0rockchip,rk3588-usb2phyÂ5 !phyclk ÷usb480m_phy0܉bm?+dpower-domain@17 5ºµ¶» x@ABdpower-domain@21�5¯®­°›š�žŸ ¡¢£¤¥¦¨§ xCDEFGHIJ+dpower-domain@235CA¯xKdpower-domain@14 5€¯­�x;dpower-domain@155…¯­x<dpower-domain@225«ªxLdpower-domain@245[Z]xMN+dpower-domain@2585çèæäßÞZxOdpower-domain@2685QxPQdpower-domain@2705ÒÓÐÏÖÕxRSTU+dpower-domain@28 5ÒÓxVWdpower-domain@29(5ÇÆÊÉÓxXYdpower-domain@305z{xZdpower-domain@31@5WŒÀ�Ž��‘x[\]^dpower-domain@33!5WZ[dpower-domain@34"5WZ[dpower-domain@37%5Š2x_dpower-domain@38&545dpower-domain@40(x`dvideo-codec@fdb50000+rockchip,rk3588-vpu121rockchip,rk3568-vpuýµÜw vdpu5±² !aclkhclka- iommu@fdb50800,rockchip,rk3588-iommurockchip,rk3568-iommuýµ@Üv !aclkiface5±²- /"arga@fdb80000(rockchip,rk3588-rgarockchip,rk3288-rgaý¸€Üt5¨§©!aclkhclksclkbrqp qos@fdf60400rockchip,rk3588-qossysconýö "?qos@fdf61000rockchip,rk3588-qossysconýö "@qos@fdf61200rockchip,rk3588-qossysconýö "Aqos@fdf61400rockchip,rk3588-qossysconýö "Bqos@fdf62000rockchip,rk3588-qossysconýö ";qos@fdf63000rockchip,rk3588-qossysconýö0 "<qos@fdf64000rockchip,rk3588-qossysconýö@ "Kqos@fdf66000rockchip,rk3588-qossysconýö` "Cqos@fdf66200rockchip,rk3588-qossysconýöb "Dqos@fdf66400rockchip,rk3588-qossysconýöd "Eqos@fdf66600rockchip,rk3588-qossysconýöf "Fqos@fdf66800rockchip,rk3588-qossysconýöh "Gqos@fdf66a00rockchip,rk3588-qossysconýöj "Hqos@fdf66c00rockchip,rk3588-qossysconýöl "Iqos@fdf66e00rockchip,rk3588-qossysconýön "Jqos@fdf67000rockchip,rk3588-qossysconýöp "Lqos@fdf67200rockchip,rk3588-qossysconýör qos@fdf70000rockchip,rk3588-qossysconý÷ "5qos@fdf71000rockchip,rk3588-qossysconý÷ "6qos@fdf72000rockchip,rk3588-qossysconý÷ "2qos@fdf72200rockchip,rk3588-qossysconý÷" "3qos@fdf72400rockchip,rk3588-qossysconý÷$ "4qos@fdf80000rockchip,rk3588-qossysconýø "Oqos@fdf81000rockchip,rk3588-qossysconýø "Pqos@fdf81200rockchip,rk3588-qossysconýø "Qqos@fdf82000rockchip,rk3588-qossysconýø "Mqos@fdf82200rockchip,rk3588-qossysconýø" "Ndfi@fe060000þrockchip,rk3588-dfi@Ü&0:²lpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcieç0?05CH>MR°)!aclk_mstaclk_slvaclk_dbipclkauxpipepciPÜø÷öõô syspmcmsglegacyerrñ`mmmm#4C0n0KJ( Opcie-phy- "Tóóó ó à@ À@0 @À@þó†dbiapbconfigb). `¥jdefault+;okayregulator@42rockchip,rk8602Bx •vdd_npu_s0¤¸Êdpâ~ðúü+regulator-state-memi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2cþª5„| !i2cpclkÜ?`¦jdefault+ ;disabledi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2cþ«5…} !i2cpclkÜ@`§jdefault+ ;disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2cþ¬5†~ !i2cpclkÜA`¨jdefault+ ;disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2cþ­5‡ !i2cpclkÜB`©jdefault+ ;disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timerþ® Ü!5TW !pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdtþ¯5dc !tclkpclkÜ;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiþ°ÜF5—’!spiclkapb_pclk3,,8txrxœ `ª«¬jdefault+ ;disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiþ±ÜG5˜“!spiclkapb_pclk3,,8txrxœ `­®¯jdefault+ ;disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiþ²ÜH5™”!spiclkapb_pclk3œœ8txrxœ`°±jdefault+;okaypmic@0rockchip,rk806£B@ ²Üjdefault`³´µ¶µÍ+Ù+å+ñ+ý+ + + !+ -+ 9+ F· S+ `¸ m¸ z+ † –dvs1-null-pins ¢gpio_pwrctrl1 §pin_fun0"´dvs2-null-pins ¢gpio_pwrctrl2 §pin_fun0"µdvs3-null-pins ¢gpio_pwrctrl3 §pin_fun0"¶regulatorsdcdc-reg1¸Êdpâ~ðú0Ô •vdd_gpu_s0 °�regulator-state-memdcdc-reg2¤¸Êdpâ~ðú0Ô•vdd_cpu_lit_s0"regulator-state-memdcdc-reg3¤¸Ê L¸â q°ú0Ô •vdd_log_s0regulator-state-mem Ì q°dcdc-reg4¤¸Êdpâ~ðú0Ô •vdd_vdenc_s0regulator-state-memdcdc-reg5¤¸Ê L¸â » ú0Ô •vdd_ddr_s0regulator-state-mem Ì øPdcdc-reg6¤¸ •vdd2_ddr_s3regulator-state-mem èdcdc-reg7¤¸Ê„€â„€ú0Ô•vdd_2v0_pldo_s3"·regulator-state-mem è Ì„€dcdc-reg8¤¸Ê2Z â2Z  •vcc_3v3_s3regulator-state-mem è Ì2Z dcdc-reg9¤¸ •vddq_ddr_s0regulator-state-memdcdc-reg10¤¸Êw@âw@ •vcc_1v8_s3regulator-state-mem è Ìw@pldo-reg1¤¸Êw@âw@ •avcc_1v8_s0regulator-state-mempldo-reg2¤¸Êw@âw@ •vcc_1v8_s0regulator-state-mem Ìw@pldo-reg3¤¸ÊO€âO€ •avdd_1v2_s0regulator-state-mempldo-reg4¤¸Ê2Z â2Z ú0Ô •vcc_3v3_s0regulator-state-mempldo-reg5¤¸Êw@â2Z ú0Ô •vccio_sd_s0regulator-state-mempldo-reg6¤¸Êw@âw@ •pldo6_s3regulator-state-mem è Ìw@nldo-reg1¤¸Ê q°â q° •vdd_0v75_s3regulator-state-mem è Ì q°nldo-reg2¤¸Ê øPâ øP•vdd_ddr_pll_s0regulator-state-mem Ì øPnldo-reg3¤¸Ê q°â q° •avdd_0v75_s0regulator-state-memnldo-reg4¤¸Ê øPâ øP •vdd_0v85_s0regulator-state-memnldo-reg5¤¸Ê q°â q° •vdd_0v75_s0regulator-state-memspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiþ³ÜI5š•!spiclkapb_pclk3œœ8txrxœ `¹º»jdefault+ ;disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartþ´ÜL5«Ÿ!baudclkapb_pclk3,, 8txrx`¼jdefaultLB ;disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartþµÜM5¯ !baudclkapb_pclk3, , 8txrx`½jdefaultLB;okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartþ¶ÜN5³¡!baudclkapb_pclk3, , 8txrx`¾jdefaultLB ;disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartþ·ÜO5·¢!baudclkapb_pclk3œ œ 8txrx`¿jdefaultLB ;disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartþ¸ÜP5»£!baudclkapb_pclk3œ œ 8txrx`ÀjdefaultLB ;disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartþ¹ÜQ5¿¤!baudclkapb_pclk3œ œ8txrx`ÁjdefaultLB ;disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartþºÜR5Ã¥!baudclkapb_pclk3kk8txrx`ÂjdefaultLB ;disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartþ»ÜS5Ǧ!baudclkapb_pclk3k k 8txrx`ÃjdefaultLB ;disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartþ¼ÜT5˧!baudclkapb_pclk3k k 8txrx`ÄjdefaultLB;okaypwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½5LK !pwmpclk`ÅjdefaultY ;disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½5LK !pwmpclk`ÆjdefaultY ;disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½ 5LK !pwmpclk`ÇjdefaultY ;disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwmþ½05LK !pwmpclk`ÈjdefaultY ;disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾5ON !pwmpclk`ÉjdefaultY ;disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾5ON !pwmpclk`ÊjdefaultY ;disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾ 5ON !pwmpclk`ËjdefaultY ;disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¾05ON !pwmpclk`ÌjdefaultY ;disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿5RQ !pwmpclk`ÍjdefaultY ;disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿5RQ !pwmpclk`ÎjdefaultY ;disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿ 5RQ !pwmpclk`ÏjdefaultY ;disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwmþ¿05RQ !pwmpclk`ÐjdefaultY ;disabledthermal-zonespackage-thermal   $Ñtripspackage-crit 4Á8 @  criticalbigcore0-thermal d  $Ñtripsbigcore0-alert 4L @Ð passive"Òbigcore0-crit 4Á8 @  criticalcooling-mapsmap0 KÒ Pÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿbigcore2-thermal d  $Ñtripsbigcore2-alert 4L @Ð passive"Óbigcore2-crit 4Á8 @  criticalcooling-mapsmap0 KÓ Pÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿlittlecore-thermal d  $Ñtripslittlecore-alert 4L @Ð passive"Ôlittlecore-crit 4Á8 @  criticalcooling-mapsmap0 KÔ0 Pÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcenter-thermal   $Ñtripscenter-crit 4Á8 @  criticalgpu-thermal d  $Ñtripsgpu-alert 4L @Ð passive"Õgpu-crit 4Á8 @  criticalcooling-mapsmap0 KÕ PÖÿÿÿÿÿÿÿÿnpu-thermal   $Ñtripsnpu-crit 4Á8 @  criticaltsadc@fec00000rockchip,rk3588-tsadcþÀÜ�5ž�!tsadcapb_pclk<žL„€bVWEÃPôvcc3v3-pcie30-regulatorregulator-fixed•vcc3v3_pcie30Ê2Z â2Z  C [jdefault` Vˆ"÷vcc5v0-sys-regulatorregulator-fixed •vcc5v0_sys¤¸ÊLK@âLK@"+vcc-1v1-nldo-s3-regulatorregulator-fixed•vcc_1v1_nldo_s3¤¸ÊÈàâÈà+"¸chosen gserial9:115200n8 compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4ethernet0mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesclock-namespower-domainsstatusdr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosiommusreg-namesrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreset-gpiosinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-moderx_delaytx_delayreset-assert-usreset-deassert-ussnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthno-sdiono-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellswakeup-sourcebitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsvpcie3v3-supplyrockchip,phy-grfopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendcooling-levelsfan-supplypwmsenable-active-highstartup-delay-usstdout-path