Ð þ팔8‚�( ‚X&firefly,roc-rk3328-ccrockchip,rk3328 +7Firefly roc-rk3328-ccaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000}/mmc@ff500000‚/mmc@ff520000cpus+cpu@0‡cpuarm,cortex-a53“—ž­½x×psciåö  cpu@1‡cpuarm,cortex-a53“—ž­½x×psciåö  cpu@2‡cpuarm,cortex-a53“—ž­½x×psciåö  cpu@3‡cpuarm,cortex-a53“—ž­½x×psciåö  idle-statespscicpu-sleeparm,idle-state*;Rxcús„l2-cache0cacheopp-table-0operating-points-v2„opp-408000000�Q––~ð¤œ@µopp-600000000�#ÃF–~ð¤œ@opp-816000000�0£,–B@¤œ@opp-1008000000�<Ü–Èज@opp-1200000000�G†Œ–±(¤œ@opp-1296000000�M?d–Ö ¤œ@analog-soundsimple-audio-cardÁi2sÚôAnalog okaysimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg' display-subsystemrockchip,display-subsystem: hdmi-soundsimple-audio-cardÁi2sÚ€ôHDMI okaysimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2Þsmctimerarm,armv8-timer0   xin24m fixed-clock@Mn6]xin24mEi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s“ÿ —)7pi2s_clki2s_hclk|  �txrx‹ okayi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s“ÿ —*8pi2s_clki2s_hclk|�txrx‹ okayi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s“ÿ —+9pi2s_clki2s_hclk|�txrx‹  disabledspdif@ff030000rockchip,rk3328-spdif“ÿ —.: pmclkhclk| �txœdefaultª‹  disabledpdm@ff040000 rockchip,pdm“ÿ—=Rppdm_clkpdm_hclk|�rxœdefaultsleepª´  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd“ÿ:io-domains"rockchip,rk3328-io-voltage-domain okay¾ÌÚèögpiorockchip,rk3328-grf-gpio/epower-controller!rockchip,rk3328-power-controller;+<power-domain@6“;power-domain@5“ —‹BAB;power-domain@8“—�F;reboot-modesyscon-reboot-modeOÈVRBÃbRBÃpRBà €RBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart“ÿ 7—&Òpbaudclkapb_pclk|�txrxœdefault ª !"Œ™  disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart“ÿ 8—'Ópbaudclkapb_pclk|�txrxœdefault ª#$%Œ™  disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart“ÿ 9—(Ôpbaudclkapb_pclk|�txrxœdefaultª&Œ™ okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ $+—7Í pi2cpclkœdefaultª'  disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ %+—8Î pi2cpclkœdefaultª( okaypmic@18rockchip,rk805“ )@]xin32krk805-clkout2/œdefaultª*£ÄÒ+Þ+ê+ö+hregulatorsDCDC_REG1 vdd_logic) ß4A Ymregulator-state-mem—B@DCDC_REG2vdd_arm) ß4A Ymregulator-state-mem—~ðDCDC_REG3vcc_ddrYmregulator-state-memDCDC_REG4vcc_io)2Z A2Z Ymregulator-state-mem—2Z LDO_REG1vcc_18)w@Aw@Ymregulator-state-mem—w@LDO_REG2 vcc18_emmc)w@Aw@Ymregulator-state-mem—w@LDO_REG3vdd_10)B@AB@Ymregulator-state-mem—B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ &+—9Ï pi2cpclkœdefaultª,  disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ '+—:Ð pi2cpclkœdefaultª-  disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi“ÿ 1+— Ñpspiclkapb_pclk| �txrxœdefaultª./01  disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt“ÿ (—ìpwm@ff1b0000rockchip,rk3328-pwm“ÿ—<Ö ppwmpclkœdefaultª2³  disabledpwm@ff1b0010rockchip,rk3328-pwm“ÿ—<Ö ppwmpclkœdefaultª3³  disabledpwm@ff1b0020rockchip,rk3328-pwm“ÿ —<Ö ppwmpclkœdefaultª4³  disabledpwm@ff1b0030rockchip,rk3328-pwm“ÿ0 2—<Ö ppwmpclkœdefaultª5³  disableddma-controller@ff1f0000arm,pl330arm,primecell“ÿ@¾—† papb_pclkÕthermal-zonessoc-thermalàöèè6tripstrip-point0&p2ÐŽpassivetrip-point1&L2ÐŽpassive7soc-crit&s2Ð Žcriticalcooling-mapsmap0=70B ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿQtsadc@ff250000rockchip,rk3328-tsadc“ÿ% :^$nÃP—$Õptsadcapb_pclkœinitdefaultsleepª8´9ƒ8�B ”tsadc-apb :­† Ä okay6efuse@ff260000rockchip,rk3328-efuse“ÿ&P+—> ppclk_efuseÚ id@7“cpu-leakage@17“logic-leakage@19“cpu-version@1a“îFadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc“ÿ( Pó—%êpsaradcapb_pclk�V ”saradc-apb  disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-450“ÿ0TZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1—‡‡ pbuscore�fiommu@ff330200rockchip,iommu“ÿ3 `—“Ý paclkiface  disablediommu@ff340800rockchip,iommu“ÿ4@ b—�F paclkiface  disabledvideo-codec@ff350000rockchip,rk3328-vpu“ÿ5  vdpu—�F paclkhclk";)<iommu@ff350800rockchip,iommu“ÿ5@  —�F paclkiface)<;video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec“ÿ6  —‹BABpaxiahbcabaccore^‹AB nׄׄá£"=)<iommu@ff360480rockchip,iommu “ÿ6€@ÿ6À@ J—‹B paclkiface)<=vop@ff370000rockchip,rk3328-vop“ÿ7>ü  —‘x;paclk_vopdclk_vophclk_vop�…†‡ ”axiahbdclk"> okayport+ endpoint@0“7?Diommu@ff373f00rockchip,iommu“ÿ7?  —‘; paclkiface okay>hdmi@ff3c0000rockchip,rk3328-dw-hdmi“ÿ<Œ#G—çFpiahbisfrcecG@Lhdmiœdefault ªABC :‹ okayportsportendpoint7D?codec@ff410000rockchip,rk3328-codec“ÿA—ë* ppclkmclk :‹ okayphy@ff430000rockchip,rk3328-hdmi-phy“ÿC S—äEypsysclkrefoclkrefpclk ]hdmi_phy@VF bcpu-versions okay@clock-controller@ff440000(rockchip,rk3328-crurockchip,crusyscon“ÿD :@~ø^x=&'(ˆ‰Ž…ƒŠŒ�ABDC"\5ˆH؉4æ$‹zEEE|n©€n6n6n6äáÀäáÀõáõáõáõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd“ÿE+usb2phy@100rockchip,rk3328-usb2phy“—Epphyclk ]usb480m_phy@^{‹G okayGotg-ports$;<=otg-bvalidotg-idlinestate okayVhost-ports > linestate okayWmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc“ÿP@   —=!JNpbiuciuciu-driveciu-sample¢­ðÑ€ okay»Å×èœdefaultªHIJKó (L4mmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc“ÿQ@   —>"KOpbiuciuciu-driveciu-sample¢­ðÑ€  disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc“ÿR@  —?#LPpbiuciuciu-driveciu-sample¢­ðÑ€ okay»ÅAN]œdefault ªMNO(4ethernet@ff540000rockchip,rk3328-gmac“ÿT macirq8—dWXZY–ßMpstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac�c ”stmmaceth :k okay^df‹PPvinputƒQŽrgmiiœdefaultªR—  )° Æ'ÃPÛæ$ïethernet@ff550000rockchip,rk3328-gmac“ÿU : macirq8—TSSU•ÞVIpstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy�b ”stmmacethŽrmiiøSkvoutput  disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22“—V�dœdefaultªTUSusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2“ÿX —Mpotghost/>€€@ GV Lusb2-phy okayusb@ff5c0000 generic-ehci“ÿ\  —NGGWLusb okayusb@ff5d0000 generic-ohci“ÿ]  —NGGWLusb okayusb@ff600000rockchip,rk3328-dwc3snps,dwc3“ÿ` C—`a„pref_clksuspend_clkbus_clkhost Mutmi_wideVw�±Òë okayinterrupt-controller@ff811000 arm,gic-400  @“ÿ�ÿ� ÿ�@ ÿ�`   pinctrlrockchip,rk3328-pinctrl :+ *gpio@ff210000rockchip,gpio-bank“ÿ! 3—È/  cgpio@ff220000rockchip,gpio-bank“ÿ" 4—É/  )gpio@ff230000rockchip,gpio-bank“ÿ# 5—Ê/  gpio@ff240000rockchip,gpio-bank“ÿ$ 6—Ë/  pcfg-pull-up 1Zpcfg-pull-down >bpcfg-pull-none MXpcfg-pull-none-2ma M Zapcfg-pull-up-2ma 1 Zpcfg-pull-up-4ma 1 Z[pcfg-pull-none-4ma M Z^pcfg-pull-down-4ma > Zpcfg-pull-none-8ma M Z\pcfg-pull-up-8ma 1 Z]pcfg-pull-none-12ma M Z _pcfg-pull-up-12ma 1 Z `pcfg-output-high ipcfg-output-low upcfg-input-high 1 €Ypcfg-input €i2c0i2c0-xfer �XX'i2c1i2c1-xfer �XX(i2c2i2c2-xfer � XX,i2c3i2c3-xfer �XX-i2c3-pins �XXhdmi_i2chdmii2c-xfer �XXBpdm-0pdmm0-clk �Xpdmm0-fsync �Xpdmm0-sdi0 �Xpdmm0-sdi1 �Xpdmm0-sdi2 �Xpdmm0-sdi3 �Xpdmm0-clk-sleep �Ypdmm0-sdi0-sleep �Ypdmm0-sdi1-sleep �Ypdmm0-sdi2-sleep �Ypdmm0-sdi3-sleep �Ypdmm0-fsync-sleep �Ytsadcotp-pin � X8otp-out � X9uart0uart0-xfer � XZ uart0-cts � X!uart0-rts � X"uart0-rts-pin � Xuart1uart1-xfer �XZ#uart1-cts �X$uart1-rts �X%uart1-rts-pin �Xuart2-0uart2m0-xfer �XZuart2-1uart2m1-xfer �XZ&spi0-0spi0m0-clk �Zspi0m0-cs0 � Zspi0m0-tx � Zspi0m0-rx � Zspi0m0-cs1 � Zspi0-1spi0m1-clk �Zspi0m1-cs0 �Zspi0m1-tx �Zspi0m1-rx �Zspi0m1-cs1 �Zspi0-2spi0m2-clk �Z.spi0m2-cs0 �Z1spi0m2-tx �Z/spi0m2-rx �Z0i2s1i2s1-mclk �Xi2s1-sclk �Xi2s1-lrckrx �Xi2s1-lrcktx �Xi2s1-sdi �Xi2s1-sdo �Xi2s1-sdio1 �Xi2s1-sdio2 �Xi2s1-sdio3 �Xi2s1-sleep� �YYYYYYYYYi2s2-0i2s2m0-mclk �Xi2s2m0-sclk �Xi2s2m0-lrckrx �Xi2s2m0-lrcktx �Xi2s2m0-sdi �Xi2s2m0-sdo �Xi2s2m0-sleep` �YYYYYYi2s2-1i2s2m1-mclk �Xi2s2m1-sclk �Xi2sm1-lrckrx �Xi2s2m1-lrcktx �Xi2s2m1-sdi �Xi2s2m1-sdo �Xi2s2m1-sleepP �YYYYYspdif-0spdifm0-tx �Xspdif-1spdifm1-tx �Xspdif-2spdifm2-tx �Xsdmmc0-0sdmmc0m0-pwren �[sdmmc0m0-pin �[sdmmc0-1sdmmc0m1-pwren �[sdmmc0m1-pin �[dsdmmc0sdmmc0-clk �\Hsdmmc0-cmd �]Isdmmc0-dectn �[Jsdmmc0-wrprt �[sdmmc0-bus1 �]sdmmc0-bus4@ �]]]]Ksdmmc0-pins€ �[[[[[[[[sdmmc0extsdmmc0ext-clk �^sdmmc0ext-cmd �[sdmmc0ext-wrprt �[sdmmc0ext-dectn �[sdmmc0ext-bus1 �[sdmmc0ext-bus4@ �[[[[sdmmc0ext-pins€ �[[[[[[[[sdmmc1sdmmc1-clk � \sdmmc1-cmd � ]sdmmc1-pwren �]sdmmc1-wrprt �]sdmmc1-dectn �]sdmmc1-bus1 �]sdmmc1-bus4@ �]]]]sdmmc1-pins� � [ [[[[[[[[emmcemmc-clk �_Memmc-cmd �`Nemmc-pwren �Xemmc-rstnout �Xemmc-bus1 �`emmc-bus4@ �````emmc-bus8€ �````````Opwm0pwm0-pin �X2pwm1pwm1-pin �X3pwm2pwm2-pin �X4pwmirpwmir-pin �X5gmac-1rgmiim1-pins` � \ ^^\^^^ ^ ^\ \^^\\\ \^\\\\Rrmiim1-pins �a_aaaa a a_ _ X XXXXXgmac2phyfephyled-speed10 �Xfephyled-duplex �Xfephyled-rxm1 �XTfephyled-txm1 �Xfephyled-linkm1 �XUtsadc_pintsadc-int � Xtsadc-pin � Xhdmi_pinhdmi-cec �XAhdmi-hpd �bCcif-0dvp-d2d9-m0À �XXXXX X X XXXXXcif-1dvp-d2d9-m1À �XXXXXXXXXXXXpmicpmic-int-l �Z*usb2usb20-host-drv �Xfchosen ›serial2:1500000n8external-gmac-clock fixed-clockMsY@ ]gmac_clkin@Pdc-12vregulator-fixeddc_12vYm)·A·gsdmmc-regulatorregulator-fixed «cœdefaultªdmvcc_sd)2Z A2Z  §Lsdmmcio-regulatorregulator-gpio ²e¶w@2Z  vcc_sdio ¸voltage)w@A2Z Y §+vcc-host1-5v-regulatorregulator-fixed Ç «)œdefaultªf vcc_host1_5vY §+vcc-sysregulator-fixedvcc_sysYm)LK@ALK@ §g+vcc-phy-regulatorregulator-fixedvcc_phyYmQleds gpio-ledsled-0 Úfirefly:blue:power àheartbeat ²h öon’#led-1 Úfirefly:yellow:user àmmc1 ²h öoff’ compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vnon-removablesnps,txpblclock_in_outphy-supplyphy-modesnps,aalsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ussnps,rxpbltx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplygpiosregulator-typeenable-active-highlabellinux,default-triggerdefault-state