Ð þ팯8‚Ì( ã‚”pine64,rock64rockchip,rk3328 +7Pine64 Rock64aliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000}/mmc@ff500000‚/mmc@ff520000cpus+cpu@0‡cpuarm,cortex-a53“—ž­½x×psciåö  cpu@1‡cpuarm,cortex-a53“—ž­½x×psciåö  cpu@2‡cpuarm,cortex-a53“—ž­½x×psciåö  cpu@3‡cpuarm,cortex-a53“—ž­½x×psciåö  idle-statespscicpu-sleeparm,idle-state*;Rxcús„l2-cache0cacheopp-table-0operating-points-v2„opp-408000000�Q––~ð¤œ@µopp-600000000�#ÃF–~ð¤œ@opp-816000000�0£,–B@¤œ@opp-1008000000�<Ü–Èज@opp-1200000000�G†Œ–±(¤œ@opp-1296000000�M?d–Ö ¤œ@analog-soundsimple-audio-cardÁi2sÚôAnalog okaysimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg' display-subsystemrockchip,display-subsystem: hdmi-soundsimple-audio-cardÁi2sÚ€ôHDMI okaysimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2Þsmctimerarm,armv8-timer0   xin24m fixed-clock@Mn6]xin24mEi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s“ÿ —)7pi2s_clki2s_hclk|  �txrx‹ okayi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s“ÿ —*8pi2s_clki2s_hclk|�txrx‹ okayi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s“ÿ —+9pi2s_clki2s_hclk|�txrx‹  disabledspdif@ff030000rockchip,rk3328-spdif“ÿ —.: pmclkhclk| �txœdefaultª‹ okayhpdm@ff040000 rockchip,pdm“ÿ—=Rppdm_clkpdm_hclk|�rxœdefaultsleepª´  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd“ÿ9io-domains"rockchip,rk3328-io-voltage-domain okay¾ÌÚèögpiorockchip,rk3328-grf-gpio/Dpower-controller!rockchip,rk3328-power-controller;+;power-domain@6“;power-domain@5“ —‹BAB;power-domain@8“—�F;reboot-modesyscon-reboot-modeOÈVRBÃbRBÃpRBà €RBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart“ÿ 7—&Òpbaudclkapb_pclk|�txrxœdefault ª !Œ™  disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart“ÿ 8—'Ópbaudclkapb_pclk|�txrxœdefault ª"#$Œ™  disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart“ÿ 9—(Ôpbaudclkapb_pclk|�txrxœdefaultª%Œ™ okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ $+—7Í pi2cpclkœdefaultª&  disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ %+—8Î pi2cpclkœdefaultª' okaypmic@18rockchip,rk805“ (@]xin32krk805-clkout2/œdefaultª)£ÄÒ*Þ*ê*ö**gregulatorsDCDC_REG1 vdd_logic) ß4A Y0Ôn‚regulator-state-mem”¬B@DCDC_REG2vdd_arm) ß4A Y0Ôn‚regulator-state-mem”¬~ðDCDC_REG3vcc_ddrn‚regulator-state-mem”DCDC_REG4vcc_io)2Z A2Z n‚regulator-state-mem”¬2Z LDO_REG1vcc_18)w@Aw@n‚regulator-state-mem”¬w@LDO_REG2 vcc18_emmc)w@Aw@n‚regulator-state-mem”¬w@LDO_REG3vdd_10)B@AB@n‚regulator-state-mem”¬B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ &+—9Ï pi2cpclkœdefaultª+  disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c“ÿ '+—:Ð pi2cpclkœdefaultª,  disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi“ÿ 1+— Ñpspiclkapb_pclk| �txrxœdefaultª-./0 okayflash@0jedec,spi-nor“Èúð€watchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt“ÿ (—ìpwm@ff1b0000rockchip,rk3328-pwm“ÿ—<Ö ppwmpclkœdefaultª1Ú  disabledpwm@ff1b0010rockchip,rk3328-pwm“ÿ—<Ö ppwmpclkœdefaultª2Ú  disabledpwm@ff1b0020rockchip,rk3328-pwm“ÿ —<Ö ppwmpclkœdefaultª3Ú  disabledpwm@ff1b0030rockchip,rk3328-pwm“ÿ0 2—<Ö ppwmpclkœdefaultª4Ú  disableddma-controller@ff1f0000arm,pl330arm,primecell“ÿ@å—† papb_pclküthermal-zonessoc-thermalè+è=5tripstrip-point0MpYÐŽpassivetrip-point1MLYÐŽpassive6soc-critMsYÐ Žcriticalcooling-mapsmap0d60i ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿxtsadc@ff250000rockchip,rk3328-tsadc“ÿ% :…$•ÃP—$Õptsadcapb_pclkœinitdefaultsleepª7´8ª7´B »tsadc-apbÇ9Ô† ë okay5efuse@ff260000rockchip,rk3328-efuse“ÿ&P+—> ppclk_efuse3 id@7“cpu-leakage@17“logic-leakage@19“cpu-version@1a“GFadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc“ÿ( PL—%êpsaradcapb_pclk´V »saradc-apb  disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-450“ÿ0TZW]XY[\"^gpgpmmupppp0ppmmu0pp1ppmmu1—‡‡ pbuscore´fiommu@ff330200rockchip,iommu“ÿ3 `—“Ý paclkifacen  disablediommu@ff340800rockchip,iommu“ÿ4@ b—�F paclkifacen  disabledvideo-codec@ff350000rockchip,rk3328-vpu“ÿ5  ^vdpu—�F paclkhclk{:‚;iommu@ff350800rockchip,iommu“ÿ5@  —�F paclkifacen‚;:video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec“ÿ6  —‹BABpaxiahbcabaccore…‹AB •ׄׄá£{<‚;iommu@ff360480rockchip,iommu “ÿ6€@ÿ6À@ J—‹B paclkifacen‚;<vop@ff370000rockchip,rk3328-vop“ÿ7>ü  —‘x;paclk_vopdclk_vophclk_vop´…†‡ »axiahbdclk{= okayport+ endpoint@0“�>Ciommu@ff373f00rockchip,iommu“ÿ7?  —‘; paclkifacen okay=hdmi@ff3c0000rockchip,rk3328-dw-hdmi“ÿ<Œ#G—çFpiahbisfrcec ?¥hdmiœdefault ª@ABÇ9‹ okayportsportendpoint�C>codec@ff410000rockchip,rk3328-codec“ÿA—ë* ppclkmclkÇ9‹ okay ¯Dphy@ff430000rockchip,rk3328-hdmi-phy“ÿC S—äEypsysclkrefoclkrefpclk ]hdmi_phy@ºF Æcpu-version× okay?clock-controller@ff440000(rockchip,rk3328-crurockchip,crusyscon“ÿDÇ9@âø…x=&'(ˆ‰Ž…ƒŠŒ�ABDC"\5ˆH؉4æ$ïzEEE|•©€n6n6n6äáÀäáÀõáõáõáõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd“ÿE+usb2phy@100rockchip,rk3328-usb2phy“—Epphyclk ]usb480m_phy@…{ïG okayGotg-port×$;<=^otg-bvalidotg-idlinestate okayVhost-port× > ^linestate okayWmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc“ÿP@   —=!JNpbiuciuciu-driveciu-sampleÌðÑ€ okay->œdefaultªHIJKILmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc“ÿQ@   —>"KOpbiuciuciu-driveciu-sampleÌðÑ€  disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc“ÿR@  —?#LPpbiuciuciu-driveciu-sampleÌðÑ€ okayUdœdefault ªMNOIrethernet@ff540000rockchip,rk3328-gmac“ÿT ^macirq8—dWXZY–ßMpstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac´c »stmmacethÇ9 okay…dfïPPŠinput—¢rgmiiœdefaultªQ« ÆRÖ ì'ÃP$ ethernet@ff550000rockchip,rk3328-gmac“ÿUÇ9 ^macirq8—TSSU•ÞVIpstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy´b »stmmaceth¢rmiiSŠoutput  disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22“—V´dœdefaultªTUSusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2“ÿX —Mpotg0host8JY€€@  V ¥usb2-phy okayusb@ff5c0000 generic-ehci“ÿ\  —NG W¥usb okayusb@ff5d0000 generic-ohci“ÿ]  —NG W¥usb okayusb@ff600000rockchip,rk3328-dwc3snps,dwc3“ÿ` C—`a„pref_clksuspend_clkbus_clk0host hutmi_wideq’ªÌí  okayinterrupt-controller@ff811000 arm,gic-400  0@“ÿ�ÿ� ÿ�@ ÿ�`   pinctrlrockchip,rk3328-pinctrlÇ9+ Egpio@ff210000rockchip,gpio-bank“ÿ! 3—È/ 0 cgpio@ff220000rockchip,gpio-bank“ÿ" 4—É/ 0 Rgpio@ff230000rockchip,gpio-bank“ÿ# 5—Ê/ 0 (gpio@ff240000rockchip,gpio-bank“ÿ$ 6—Ë/ 0 pcfg-pull-up LZpcfg-pull-down Ybpcfg-pull-none hXpcfg-pull-none-2ma h uapcfg-pull-up-2ma L upcfg-pull-up-4ma L u[pcfg-pull-none-4ma h u^pcfg-pull-down-4ma Y upcfg-pull-none-8ma h u\pcfg-pull-up-8ma L u]pcfg-pull-none-12ma h u _pcfg-pull-up-12ma L u `pcfg-output-high „pcfg-output-low �pcfg-input-high L ›Ypcfg-input ›i2c0i2c0-xfer ¨XX&i2c1i2c1-xfer ¨XX'i2c2i2c2-xfer ¨ XX+i2c3i2c3-xfer ¨XX,i2c3-pins ¨XXhdmi_i2chdmii2c-xfer ¨XXApdm-0pdmm0-clk ¨Xpdmm0-fsync ¨Xpdmm0-sdi0 ¨Xpdmm0-sdi1 ¨Xpdmm0-sdi2 ¨Xpdmm0-sdi3 ¨Xpdmm0-clk-sleep ¨Ypdmm0-sdi0-sleep ¨Ypdmm0-sdi1-sleep ¨Ypdmm0-sdi2-sleep ¨Ypdmm0-sdi3-sleep ¨Ypdmm0-fsync-sleep ¨Ytsadcotp-pin ¨ X7otp-out ¨ X8uart0uart0-xfer ¨ XZuart0-cts ¨ X uart0-rts ¨ X!uart0-rts-pin ¨ Xuart1uart1-xfer ¨XZ"uart1-cts ¨X#uart1-rts ¨X$uart1-rts-pin ¨Xuart2-0uart2m0-xfer ¨XZuart2-1uart2m1-xfer ¨XZ%spi0-0spi0m0-clk ¨Zspi0m0-cs0 ¨ Zspi0m0-tx ¨ Zspi0m0-rx ¨ Zspi0m0-cs1 ¨ Zspi0-1spi0m1-clk ¨Zspi0m1-cs0 ¨Zspi0m1-tx ¨Zspi0m1-rx ¨Zspi0m1-cs1 ¨Zspi0-2spi0m2-clk ¨Z-spi0m2-cs0 ¨Z0spi0m2-tx ¨Z.spi0m2-rx ¨Z/i2s1i2s1-mclk ¨Xi2s1-sclk ¨Xi2s1-lrckrx ¨Xi2s1-lrcktx ¨Xi2s1-sdi ¨Xi2s1-sdo ¨Xi2s1-sdio1 ¨Xi2s1-sdio2 ¨Xi2s1-sdio3 ¨Xi2s1-sleep� ¨YYYYYYYYYi2s2-0i2s2m0-mclk ¨Xi2s2m0-sclk ¨Xi2s2m0-lrckrx ¨Xi2s2m0-lrcktx ¨Xi2s2m0-sdi ¨Xi2s2m0-sdo ¨Xi2s2m0-sleep` ¨YYYYYYi2s2-1i2s2m1-mclk ¨Xi2s2m1-sclk ¨Xi2sm1-lrckrx ¨Xi2s2m1-lrcktx ¨Xi2s2m1-sdi ¨Xi2s2m1-sdo ¨Xi2s2m1-sleepP ¨YYYYYspdif-0spdifm0-tx ¨Xspdif-1spdifm1-tx ¨Xspdif-2spdifm2-tx ¨Xsdmmc0-0sdmmc0m0-pwren ¨[sdmmc0m0-pin ¨[sdmmc0-1sdmmc0m1-pwren ¨[sdmmc0m1-pin ¨[dsdmmc0sdmmc0-clk ¨\Hsdmmc0-cmd ¨]Isdmmc0-dectn ¨[Jsdmmc0-wrprt ¨[sdmmc0-bus1 ¨]sdmmc0-bus4@ ¨]]]]Ksdmmc0-pins€ ¨[[[[[[[[sdmmc0extsdmmc0ext-clk ¨^sdmmc0ext-cmd ¨[sdmmc0ext-wrprt ¨[sdmmc0ext-dectn ¨[sdmmc0ext-bus1 ¨[sdmmc0ext-bus4@ ¨[[[[sdmmc0ext-pins€ ¨[[[[[[[[sdmmc1sdmmc1-clk ¨ \sdmmc1-cmd ¨ ]sdmmc1-pwren ¨]sdmmc1-wrprt ¨]sdmmc1-dectn ¨]sdmmc1-bus1 ¨]sdmmc1-bus4@ ¨]]]]sdmmc1-pins� ¨ [ [[[[[[[[emmcemmc-clk ¨_Memmc-cmd ¨`Nemmc-pwren ¨Xemmc-rstnout ¨Xemmc-bus1 ¨`emmc-bus4@ ¨````emmc-bus8€ ¨````````Opwm0pwm0-pin ¨X1pwm1pwm1-pin ¨X2pwm2pwm2-pin ¨X3pwmirpwmir-pin ¨X4gmac-1rgmiim1-pins` ¨ \ ^^\^^^ ^ ^\ \^^\\\ \^\\\\Qrmiim1-pins ¨a_aaaa a a_ _ X XXXXXgmac2phyfephyled-speed10 ¨Xfephyled-duplex ¨Xfephyled-rxm1 ¨XTfephyled-txm1 ¨Xfephyled-linkm1 ¨XUtsadc_pintsadc-int ¨ Xtsadc-pin ¨ Xhdmi_pinhdmi-cec ¨X@hdmi-hpd ¨bBcif-0dvp-d2d9-m0À ¨XXXXX X X XXXXXcif-1dvp-d2d9-m1À ¨XXXXXXXXXXXXirir-int ¨Xfpmicpmic-int-l ¨Z)usb2usb20-host-drv ¨Xechosen ¶serial2:1500000n8external-gmac-clock fixed-clockMsY@ ]gmac_clkin@Psdmmc-regulatorregulator-fixed Ñcœdefaultªdvcc_sd)2Z A2Z  ÂLvcc-host-5v-regulatorregulator-fixed Ñcœdefaultªe vcc_host_5vn‚ Â*vcc-host1-5v-regulatorregulator-fixed Ñcœdefaultªe vcc_host1_5vn‚ Â*vcc-sysregulator-fixedvcc_sysn‚)LK@ALK@*ir-receivergpio-ir-receiver ´(ªfœdefaultleds gpio-ledsled-0 ´g Ímmc0led-1 ´g Íheartbeatspdif-soundsimple-audio-cardôSPDIFsimple-audio-card,cpuhsimple-audio-card,codecispdif-ditlinux,spdif-dit‹i compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltspi-max-frequency#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesmute-gpiosnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplymmc-hs200-1_8vnon-removablevqmmc-supplysnps,txpblclock_in_outphy-supplyphy-modesnps,force_thresh_dma_modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplylinux,default-trigger