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 Bapb_pclk×Gi2c@ff650000(rockchip,rk3368-i2crockchip,rk3288-i2c¶ÿe; LBi2c ß<Ôdefaultâ.+lokaypmic@1brockchip,rk808¶ /ßÔdefaultâ0192E2Q2]2i2u2��2™2¦2³ xin32krk808-clkout2 regulatorsDCDC_REG1ÀÔæ ®`þã`vdd_cpuDCDC_REG2ÀÔæ ®`þã`vdd_logDCDC_REG3ÀÔvcc_ddrDCDC_REG4ÀÔæ2Z þ2Z vcc_io×LDO_REG1ÀÔæw@þw@ vcc18_flash×LDO_REG2ÀÔæ2Z þ2Z vcca_33LDO_REG3ÀÔæB@þB@vdd_10LDO_REG4æ2Z þ2Z avdd_33LDO_REG5ÀÔæw@þ2Z  vccio_sd×LDO_REG6ÀÔæB@þB@ vdd10_lcdLDO_REG7ÀÔæw@þw@vcc_18LDO_REG8ÀÔæw@þw@ vcc18_lcdSWITCH_REG1vcc_sd×SWITCH_REG2ÀÔ vcc33_lcdi2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2c¶ÿf ß=+Bi2c; MÔdefaultâ3lokayaccelerometer@18 bosch,bma250¶ 4ßpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwm¶ÿh%Ôdefaultâ5; _ ldisabledpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwm¶ÿh%Ôdefaultâ6; _ ldisabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwm¶ÿh %; _ ldisabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwm¶ÿh0%Ôdefaultâ7; _ ldisabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uart¶ÿi; O WBbaudclkapb_pclk ß9Ôdefaultâ8�§ ldisabledmbox@ff6b0000rockchip,rk3368-mailbox¶ÿk0ß’“”•; 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R Ï¡GG¦txrxÔdefaultâI ldisablediommu@ff900800rockchip,iommu¶ÿ� ß; Ê Ô Baclkiface°J ¾ ldisablediommu@ff914000rockchip,iommu ¶ÿ‘@ÿ‘P ß; Í Õ Baclkiface¾°J Ë ldisablediommu@ff930300rockchip,iommu¶ÿ“ ß; Æ Ñ Baclkiface°J ¾ ldisablediommu@ff9a0440rockchip,iommu ¶ÿš@@ÿš€@ ß ; Ð Ü Baclkiface¾ ldisablediommu@ff9a0800rockchip,iommu¶ÿšß  ; Ð Ü Baclkiface¾ ldisabledqos@ffad0000rockchip,rk3368-qossyscon¶ÿ­ ×9qos@ffad0080rockchip,rk3368-qossyscon¶ÿ­€ ×:qos@ffad0100rockchip,rk3368-qossyscon¶ÿ­ ×;qos@ffad0180rockchip,rk3368-qossyscon¶ÿ­€ ×<qos@ffad0200rockchip,rk3368-qossyscon¶ÿ­ ×=qos@ffad0280rockchip,rk3368-qossyscon¶ÿ­€ ×>qos@ffad0300rockchip,rk3368-qossyscon¶ÿ­ ×?qos@ffad0380rockchip,rk3368-qossyscon¶ÿ­€ ×@qos@ffad0400rockchip,rk3368-qossyscon¶ÿ­ ×Aqos@ffae0000rockchip,rk3368-qossyscon¶ÿ® ×Bqos@ffae0100rockchip,rk3368-qossyscon¶ÿ® ×Cqos@ffae0180rockchip,rk3368-qossyscon¶ÿ®€ ×Dqos@ffaf0000rockchip,rk3368-qossyscon¶ÿ¯ ×Eefuse@ffb00000rockchip,rk3368-efuse¶ÿ° +; q Bpclk_efusecpu-leakage@17¶temp-adjust@1f¶interrupt-controller@ffb71000 arm,gic-400æû@¶ÿ·ÿ· ÿ·@ ÿ·`  ß ÿ×pinctrlrockchip,rk3368-pinctrlÓ- K+gpio@ff750000rockchip,gpio-bank¶ÿu; @ ßQ 0æû×/gpio@ff780000rockchip,gpio-bank¶ÿx; A ßR 0æûgpio@ff790000rockchip,gpio-bank¶ÿy; B ßS 0æû×4gpio@ff7a0000rockchip,gpio-bank¶ÿz; C ßT 0æû×#pcfg-pull-up<×Mpcfg-pull-downIpcfg-pull-noneX×Lpcfg-pull-none-12maXe ×Nemmcemmc-clktL×emmc-cmdtM×emmc-pwrtMemmc-bus1tMemmc-bus4@tMMMMemmc-bus8€tMMMMMMMM×gmacrgmii-pinsðtLLLN N NNN NLLLLLLrmii-pins tLLLN N NLLLLi2c0i2c0-xfer tLL×.i2c1i2c1-xfer tLL×3i2c2i2c2-xfer t LL×"i2c3i2c3-xfer tLL×$i2c4i2c4-xfer tLL×%i2c5i2c5-xfer tLL×&i2si2s-8ch-bus�t L LLLLLLLL×Ipwm0pwm0-pintL×5pwm1pwm1-pintL×6pwm3pwm3-pintL×7sdio0sdio0-bus1tMsdio0-bus4@tMMMMsdio0-cmdtMsdio0-clktLsdio0-cdtMsdio0-wptMsdio0-pwrtMsdio0-bkpwrtMsdio0-inttMsdmmcsdmmc-clkt L× sdmmc-cmdt M× sdmmc-cdt M×sdmmc-bus1tMsdmmc-bus4@tMMMM× spdifspdif-txtL×Hspi0spi0-clktM×spi0-cs0tM×spi0-cs1tMspi0-txtM×spi0-rxtM×spi1spi1-clktM×spi1-cs0tM×spi1-cs1tMspi1-rxtM×spi1-txtM×spi2spi2-clkt M×spi2-cs0t M×!spi2-rxt M× spi2-txt M×tsadcotp-pintL×+otp-outtL×,uart0uart0-xfer tMLuart0-ctstLuart0-rtstLuart1uart1-xfer tMLuart1-ctstLuart1-rtstLuart2uart2-xfer tML×8uart3uart3-xfer tMLuart3-ctstLuart3-rtstLuart4uart4-xfer tMLuart4-ctstLuart4-rtstLkeyspwr-keytL×Opmicpmic-sleeptL×1pmic-inttM×0chosen‚serial4:115200n8memory@0¶@ªmemorygpio-keys gpio-keysÔdefaultâOpower ^/ ŽGPIO Power”tŸvcc-sys-regulatorregulator-fixedvcc_sysæLK@þLK@ÀÔ×2 compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1cpudevice_typeregenable-method#cooling-cellsphandleinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delayno-sdiosd-uhs-sdr12sd-uhs-sdr25pinctrl-namespinctrl-0rockchip,default-sample-phasevmmc-supplyvqmmc-supplymmc-hs200-1_8vno-sdnon-removable#io-channel-cellspower-gpiostouchscreen-size-xtouchscreen-size-ysilead,max-fingersreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-name#pwm-cells#mbox-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-namespower-domains#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathlabellinux,codewakeup-source