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Æ Ñ BaclkifaceÑH ß ldisablediommu@ff9a0440rockchip,iommu ¶ÿš@@ÿš€@ ß ; Ð Ü Baclkifaceß ldisablediommu@ff9a0800rockchip,iommu¶ÿšß  ; Ð Ü Baclkifaceß ldisabledqos@ffad0000rockchip,rk3368-qossyscon¶ÿ­ ×7qos@ffad0080rockchip,rk3368-qossyscon¶ÿ­€ ×8qos@ffad0100rockchip,rk3368-qossyscon¶ÿ­ ×9qos@ffad0180rockchip,rk3368-qossyscon¶ÿ­€ ×:qos@ffad0200rockchip,rk3368-qossyscon¶ÿ­ ×;qos@ffad0280rockchip,rk3368-qossyscon¶ÿ­€ ×<qos@ffad0300rockchip,rk3368-qossyscon¶ÿ­ ×=qos@ffad0380rockchip,rk3368-qossyscon¶ÿ­€ ×>qos@ffad0400rockchip,rk3368-qossyscon¶ÿ­ ×?qos@ffae0000rockchip,rk3368-qossyscon¶ÿ® ×@qos@ffae0100rockchip,rk3368-qossyscon¶ÿ® ×Aqos@ffae0180rockchip,rk3368-qossyscon¶ÿ®€ ×Bqos@ffaf0000rockchip,rk3368-qossyscon¶ÿ¯ ×Cefuse@ffb00000rockchip,rk3368-efuse¶ÿ° +; q Bpclk_efusecpu-leakage@17¶temp-adjust@1f¶interrupt-controller@ffb71000 arm,gic-400@¶ÿ·ÿ· ÿ·@ ÿ·`  ß ÿ×pinctrlrockchip,rk3368-pinctrlˆ,-I+:gpio@ff750000rockchip,gpio-bank¶ÿu; @ ßQAQ×Rgpio@ff780000rockchip,gpio-bank¶ÿx; A ßRAQgpio@ff790000rockchip,gpio-bank¶ÿy; B ßSAQ×Pgpio@ff7a0000rockchip,gpio-bank¶ÿz; C ßTAQ×.pcfg-pull-up]×Lpcfg-pull-downjpcfg-pull-noney×Mpcfg-pull-none-12may† ×Nemmcemmc-clk•J×emmc-cmd•K×emmc-pwr•Lemmc-bus1•Lemmc-bus4@•LLLLemmc-bus8€•KKKKKKKK×emmc-reset•M×Ogmacrgmii-pinsð•MMMN N NNN NMMMMMMrmii-pins •MMMN N NMMMM×/i2c0i2c0-xfer •MM×0i2c1i2c1-xfer •MM×2i2c2i2c2-xfer • MM×"i2c3i2c3-xfer •MM×#i2c4i2c4-xfer •MM×$i2c5i2c5-xfer •MM×%i2si2s-8ch-bus�• M MMMMMMMM×Gpwm0pwm0-pin•M×3pwm1pwm1-pin•M×4pwm3pwm3-pin•M×5sdio0sdio0-bus1•Lsdio0-bus4@•LLLL×sdio0-cmd•L× sdio0-clk•M× sdio0-cd•Lsdio0-wp•Lsdio0-pwr•Lsdio0-bkpwr•Lsdio0-int•Lsdmmcsdmmc-clk• Msdmmc-cmd• Lsdmmc-cd• Lsdmmc-bus1•Lsdmmc-bus4@•LLLLspdifspdif-tx•M×Fspi0spi0-clk•L×spi0-cs0•L×spi0-cs1•Lspi0-tx•L×spi0-rx•L×spi1spi1-clk•L×spi1-cs0•L×spi1-cs1•Lspi1-rx•L×spi1-tx•L×spi2spi2-clk• L×spi2-cs0• L×!spi2-rx• L× spi2-tx• L×tsadcotp-pin•M×*otp-out•M×+uart0uart0-xfer •LMuart0-cts•Muart0-rts•Muart1uart1-xfer •LMuart1-cts•Muart1-rts•Muart2uart2-xfer •LM×6uart3uart3-xfer •LMuart3-cts•Muart3-rts•Muart4uart4-xfer •LMuart4-cts•Muart4-rts•Mpcfg-pull-none-drv-8may†×Jpcfg-pull-up-drv-8ma]†×Kirir-int•L×Tkeyspwr-key•L×Qledsstby-pwren• Mled-ctl•M×Ssdiowifi-reg-on•M×Wbt-rst•M×Vusbhost-vbus-drv•M×Xchosen£serial2:115200n8memoryªmemory¶@emmc-pwrseqmmc-pwrseq-emmcÿOñdefault ¯P×gpio-keys gpio-keysñdefaultÿQpower» µR ÉGPIO PowerÏtgpio-leds gpio-ledsled-0 µ.Ér88:green:ledñdefaultÿSir-receivergpio-ir-receiver µ.ñdefaultÿTsdio-pwrseqmmc-pwrseq-simple;U Bext_clockñdefaultÿVW¯..× vcc18-regulatorregulator-fixedXvcc_18ƒw@›w@ÈÜî1×vcc-host-regulatorregulator-fixedÚ ÁRñdefaultÿX Xvcc_hostÈÜî1vcc-io-regulatorregulator-fixedXvcc_ioƒ2Z ›2Z ÈÜî1×vcc-lan-regulatorregulator-fixedXvcc_lanƒ2Z ›2Z ÈÜî×-vcc-sys-regulatorregulator-fixedXvcc_sysƒLK@›LK@ÈÜ×1vccio-wl-regulatorregulator-fixed Xvccio_wlƒ2Z ›2Z ÈÜî×vdd-10-regulatorregulator-fixedXvdd_10ƒB@›B@ÈÜî1 compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1cpudevice_typeregenable-method#cooling-cellsphandleinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesstatusassigned-clocksassigned-clock-parentsbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-mmc-highspeed#io-channel-cellsvref-supplyreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supply#pwm-cells#mbox-cells#power-domain-cellspm_qospmu-supplyvop-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsaudio-supplygpio30-supplygpio1830-supplywifi-supplydmasdma-namespower-domains#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathreset-gpioswakeup-sourcelabellinux,codeenable-active-high