Ð þí·8ôˆ(/ôPRgoogle,scarlet-rev15-sku6google,scarlet-rev15google,scarlet-rev14-sku6google,scarlet-rev14google,scarlet-rev13-sku6google,scarlet-rev13google,scarlet-rev12-sku6google,scarlet-rev12google,scarlet-rev11-sku6google,scarlet-rev11google,scarlet-rev10-sku6google,scarlet-rev10google,scarlet-rev9-sku6google,scarlet-rev9google,scarlet-rev8-sku6google,scarlet-rev8google,scarlet-rev7-sku6google,scarlet-rev7google,scarlet-rev6-sku6google,scarlet-rev6google,scarlet-rev5-sku6google,scarlet-rev5google,scarlet-rev4-sku6google,scarlet-rev4google,scarletgoogle,grurockchip,rk3399 +7tabletDGoogle ScarletaliasesJ/ethernet@fe300000T/i2c@ff3c0000Y/i2c@ff110000^/i2c@ff120000c/i2c@ff130000h/i2c@ff3d0000m/i2c@ff140000r/i2c@ff150000w/i2c@ff160000|/i2c@ff3e0000�/serial@ff180000‰/serial@ff190000‘/serial@ff1a0000™/serial@ff1b0000¡/serial@ff370000©/mmc@fe320000®/mmc@fe330000cpus+cpu-mapcluster0core0³core1³core2³core3³cluster1core0³core1³cpu@0·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@1·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@2·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@3·cpuarm,cortex-a53ÃÇpsciÕåèïþd ( < Gcpu@100·cpuarm,cortex-a72ÃÇpsciÕè ïþ´ ( <Gthermal-idleïO'[ôcpu@101·cpuarm,cortex-a72ÃÇpsciÕè ïþ´ ( <Gthermal-idleïO'[ôidle-stateskpscicpu-sleeparm,idle-statex‰ x[ú±„G cluster-sleeparm,idle-statex‰ �[ô±ÐG display-subsystemrockchip,display-subsystemÂmemory-controllerrockchip,rk3399-dmcÈÕè¨ädmc_clkðokay(÷  ( ;ðV@o'²Z€Š'²Z€§'²Z€Ä;šÊé 7P(/pmu_a53arm,cortex-a53-pmu=pmu_a72arm,cortex-a72-pmu=psci arm,psci-1.0Îsmctimerarm,armv8-timer@=   Hxin24m fixed-clock_n6oxin24m‚G“pcie@f8000000rockchip,rk3399-pcie Ãøý�axi-baseapb-base·pci+™ª¶ èÅÄG äaclkaclk-perfhclkpm0=123ÀsyslegacyclientÐ`ãñ , pcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-38‚úúà�ûàûà8‚ƒ„…†�€(%coremgmtmgmt-stickypipepmpclkaclkðokay 1:defaultHRbr‚interrupt-controller•™Gpcie@0,0Ã+ethernet@fe300000rockchip,rk3399-gmacÃþ0= Àmacirq8èighfjÕfMästmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macª‰ %stmmaceth¸ Å ðdisabledmmc@fe3100000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshcÃþ1@=@ÐðÑ€ èîMœ�äbiuciuciu-driveciu-sampleÞªy%reset ðdisabledmmc@fe3200000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshcÃþ2@=AÐðÑ€éÍù ë èÎLš›äbiuciuciu-driveciu-sampleÞªz%resetðokay:defaultH!"#$%* ;& DO\iv„'�(mmc@fe330000+rockchip,rk3399-sdhci-5.1arasan,sdhci-5.1Ãþ3= � éNùðÑ€èNðäclk_xinclk_ahboemmc_cardclock‚)  phy_arasanª³ðokayÄÓíG”usb@fe380000 generic-ehciÃþ8=èÈÉ*+ usb ðdisabledusb@fe3a0000 generic-ohciÃþ:=èÈÉ*+ usbðokay+bluetooth@1usbcf3,e300usb4ca,301aÃ:defaultH, &=Àwakeupusb@fe3c0000 generic-ehciÃþ<=èÊË-. usb ðdisabledusb@fe3e0000 generic-ohciÃþ>= èÊË-. usb ðdisableddebug@fe430000&arm,coresight-cpu-debugarm,primecellÃþCèM äapb_pclk³debug@fe432000&arm,coresight-cpu-debugarm,primecellÃþC èM äapb_pclk³debug@fe434000&arm,coresight-cpu-debugarm,primecellÃþC@èM äapb_pclk³debug@fe436000&arm,coresight-cpu-debugarm,primecellÃþC`èM äapb_pclk³debug@fe610000&arm,coresight-cpu-debugarm,primecellÃþaèL äapb_pclk³debug@fe710000&arm,coresight-cpu-debugarm,primecellÃþqèL äapb_pclk³usb@fe800000rockchip,rk3399-dwc3+0è�ƒöøôùGäref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk% %usb3-otgðokayû/usb@fe800000 snps,dwc3Ãþ€=iè�öƒärefbus_earlysuspendhost01 usb2-phyusb3-phy  utmi_wide+Le†ªðokayusb@fe900000rockchip,rk3399-dwc3+0è‚„÷øôùGäref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk& %usb3-otg ðdisabledusb@fe900000 snps,dwc3Ãþ�=nè‚÷„ärefbus_earlysuspendotg23 usb2-phyusb3-phy  utmi_wide+Le†ª ðdisableddp@fec00000rockchip,rk3399-cdn-dpÃþÀ= ér¡ùõá ë èru¡oäcore-clkpclkspdifgrf4ª HJý%spdifdptxapbcore¸ ¨ðokayû/GÚportsport+endpoint@0ù5G¢endpoint@1ù6Gœinterrupt-controller@fee00000 arm,gic-v3™+•PÃþàþð ÿðÿñÿò= Ginterrupt-controller@fee20000arm,gic-v3-itsÉØÃþâGppi-partitionsinterrupt-partition-0ãGinterrupt-partition-1ãGsaradc@ff100000rockchip,rk3399-saradcÃÿ=>ìèPeäsaradcapb_pclkÔ %saradc-apb ðdisabledi2c@ff110000rockchip,rk3399-i2cÃÿéAù ëÂèAU äi2cpclk=;:defaultH7+ ðdisabledi2c@ff120000rockchip,rk3399-i2cÃÿéBù ëÂèBV äi2cpclk=#:defaultH8+ðokay_€þ2,digitizer@9 hid-over-i2cà  &=-:defaultH9:i2c@ff130000rockchip,rk3399-i2cÃÿéCù ëÂèCW äi2cpclk=":defaultH;+ðokay_€þ2,touchscreen@10elan,ekth3500à &=:defaultH<= < i2c@ff140000rockchip,rk3399-i2cÃÿéDù ëÂèDX äi2cpclk=&:defaultH>+ ðdisabledi2c@ff150000rockchip,rk3399-i2cÃÿéEù ëÂèEY äi2cpclk=%:defaultH?+ ðdisabledi2c@ff160000rockchip,rk3399-i2cÃÿéFù ëÂèFZ äi2cpclk=$:defaultH@A+ðokay_€þ2,camera@36 ovti,ov5695Ã6:defaultHBè©äxvclkHCTD` <Eportendpoint¹FmG¥camera@3c ovti,ov2685Ã<:defaultHGè©äxvclkHC`T <Eportendpoint¹HmG¦serial@ff180000&rockchip,rk3399-uartsnps,dw-apb-uartÃÿèQ`äbaudclkapb_pclk=cx‚:defaultHI ðdisabledserial@ff190000&rockchip,rk3399-uartsnps,dw-apb-uartÃÿèRaäbaudclkapb_pclk=bx‚:defaultHJ ðdisabledserial@ff1a0000&rockchip,rk3399-uartsnps,dw-apb-uartÃÿèSbäbaudclkapb_pclk=dx‚:defaultHKðokayserial@ff1b0000&rockchip,rk3399-uartsnps,dw-apb-uartÃÿèTcäbaudclkapb_pclk=ex‚:defaultHL ðdisabledspi@ff1c0000(rockchip,rk3399-spirockchip,rk3066-spiÃÿèG[äspiclkapb_pclk=D�M M ”txrx:defaultHNOPQ+ ðdisabledspi@ff1d0000(rockchip,rk3399-spirockchip,rk3066-spiÃÿèH\äspiclkapb_pclk=5�M M ”txrx:defaultsleepHRSTU+ðokayžVflash@0jedec,spi-nor蘖€spi@ff1e0000(rockchip,rk3399-spirockchip,rk3066-spiÃÿèI]äspiclkapb_pclk=4�MM”txrx:defaultHWXYZ+ðokaycr50@0 google,cr50à &=:defaultH[¨ 5spi@ff1f0000(rockchip,rk3399-spirockchip,rk3066-spiÃÿèJ^äspiclkapb_pclk=C�MM”txrx:defaultH\]^_+ ðdisabledspi@ff200000(rockchip,rk3399-spirockchip,rk3066-spiÃÿ èK_äspiclkapb_pclk=„�`` ”txrx:defaultHabcdª+ðokayec@0google,cros-ec-spià &=:defaultHe¨-ÆÀi2c-tunnelgoogle,cros-ec-i2c-tunnelº+sbs-battery@bsbs,sbs-batteryà Ìàextcon0google,extcon-usbc-cros-ecõG/keyboard-controllergoogle,cros-ec-keyb +DE;<=>?@A B CD}0Y1 d"#(  \V |})  Ž + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ithermal-zonescpu-thermalRdhèvftripscpu_alert0†Ð’Ð?passiveGgcpu_alert1†X’Ð?passiveGhcpu_crit†s’Ð ?criticalcooling-mapsmap0�g¢ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1�hH¢ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿgpu-thermalRdhèvftripsgpu_alert0†$ø’Ð?passiveGigpu_crit†s’Ð ?criticalcooling-mapsmap0�i ¢jÿÿÿÿÿÿÿÿtsadc@ff260000rockchip,rk3399-tsadcÃÿ&=aéOù q°èOdätsadcapb_pclkè %tsadc-apb¸ ±s:initdefaultsleepHkžlÈkÒðokayèÿGfqos@ffa58000rockchip,rk3399-qossysconÃÿ¥€ Gtqos@ffa5c000rockchip,rk3399-qossysconÃÿ¥À Guqos@ffa60080rockchip,rk3399-qossysconÃÿ¦€ qos@ffa60100rockchip,rk3399-qossysconÃÿ¦ qos@ffa60180rockchip,rk3399-qossysconÃÿ¦€ qos@ffa70000rockchip,rk3399-qossysconÃÿ§ Gxqos@ffa70080rockchip,rk3399-qossysconÃÿ§€ Gyqos@ffa74000rockchip,rk3399-qossysconÃÿ§@ Gvqos@ffa76000rockchip,rk3399-qossysconÃÿ§` Gwqos@ffa90000rockchip,rk3399-qossysconÃÿ© Gzqos@ffa98000rockchip,rk3399-qossysconÃÿ©€ Gmqos@ffaa0000rockchip,rk3399-qossysconÃÿª G{qos@ffaa0080rockchip,rk3399-qossysconÃÿª€ G|qos@ffaa8000rockchip,rk3399-qossysconÃÿª€ G}qos@ffaa8080rockchip,rk3399-qossysconÃÿª€€ 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syscon@ff320000)rockchip,rk3399-pmugrfsysconsimple-mfdÃÿ2Gio-domains&rockchip,rk3399-pmu-io-voltage-domainðokay 5spi@ff350000(rockchip,rk3399-spirockchip,rk3066-spiÃÿ5è‚‚äspiclkapb_pclk=<:defaultHƒ„…†+ ðdisabledserial@ff370000&rockchip,rk3399-uartsnps,dw-apb-uartÃÿ7è‚‚"äbaudclkapb_pclk=fx‚:defaultH‡ ðdisabledi2c@ff3c0000rockchip,rk3399-i2cÃÿ<é‚ ù ëÂè‚ ‚ äi2cpclk=9:defaultHˆ+ ðdisabledi2c@ff3d0000rockchip,rk3399-i2cÃÿ=é‚ ù ëÂè‚ ‚ äi2cpclk=8:defaultH‰+ ðdisabledi2c@ff3e0000rockchip,rk3399-i2cÃÿ>é‚ ù ëÂè‚ ‚ äi2cpclk=::defaultHŠ+ðokay_€þ2,da7219@1a dlg,da7219à &=èYämclk D ( Tdiff:defaultH‹ g rŒ €GÙda7219_aad � ž ª2 ¶ô Æ ×32ms_64ms é ú   ! *>pwm@ff420000(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB <:defaultH�è‚ðokayGÏpwm@ff420010(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB <:defaultHŽè‚ðokayGäpwm@ff420020(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB  <:defaultH�è‚ðokayGÍpwm@ff420030(rockchip,rk3399-pwmrockchip,rk3288-pwmÃÿB0 <:defaultH�è‚ðokayGËdfi@ff630000Ãÿc@rockchip,rk3399-dfiÈ=ƒèy äpclk_ddr_monðokayGvideo-codec@ff650000rockchip,rk3399-vpuÃÿe =rq Àvepuvdpuèëê äaclkhclk G‘ªiommu@ff650800rockchip,iommuÃÿe@=sèëê äaclkiface NªG‘video-codec@ff660000rockchip,rk3399-vdecÃÿf=t èí쟞äaxiahbcabaccore G’ª iommu@ff660480rockchip,iommu Ãÿf€@ÿfÀ@=uèíì äaclkifaceª  NG’iommu@ff670800rockchip,iommuÃÿg@=*èáÝ äaclkiface N ðdisabledrga@ff680000rockchip,rk3399-rgaÃÿh=7èÜåmäaclkhclksclkjgi %coreaxiahbª!efuse@ff690000rockchip,rk3399-efuseÃÿi€+è} äpclk_efusecpu-id@7Ãcpu-leakage@17Ãgpu-leakage@18Ãcenter-leakage@19Ãcpu-leakage@1aÃlogic-leakage@1bÃwafer-info@1cÃdma-controller@ff6d0000arm,pl330arm,primecellÃÿm@ = [ fèÓ äapb_pclkG`dma-controller@ff6e0000arm,pl330arm,primecellÃÿn@ = [ fèÔ äapb_pclkGMclock-controller@ff750000rockchip,rk3399-pmucruÃÿuè“äxin24m¸‚ }é‚ù(JñG‚clock-controller@ff760000rockchip,rk3399-cruÃÿvè“äxin24m¸ ‚ }ˆéÀÀ@ÂÁBÉÂCãxÞíDù#ÃF_^;šÊðÑ€xhÀ<4`õáõáúð€/¯õáúð€ׄ ë ëÂׄׄGsyscon@ff770000&rockchip,rk3399-grfsysconsimple-mfdÃÿw+G io-domains"rockchip,rk3399-io-voltage-domainðokay Š — ¤ ´(mipi-dphy-rx0rockchip,rk3399-mipi-dphy-rx0èw¥oädphy-refdphy-cfggrfª ÁðokayG¤usb2phy@e450rockchip,rk3399-usb2phyÃäPè{äphyclk‚oclk_usbphy0_480mðokayG*host-port Á= ÀlinestateðokayG+otg-port Á0=ghjÀotg-bvalidotg-idlinestateðokayG0usb2phy@e460rockchip,rk3399-usb2phyÃä`è|äphyclk‚oclk_usbphy1_480m ðdisabledG-host-port Á= ÀlinestateðokayG.otg-port Á0=lmoÀotg-bvalidotg-idlinestateðokayG2phy@f780rockchip,rk3399-emmc-phyÃ÷€$è”äemmcclk Ì2 ÁðokayG)pcie-phyrockchip,rk3399-pcie-phyèŠärefclk Á‡%phyðokayGphy@ff7c0000rockchip,rk3399-typec-phyÃÿ|è~}ätcpdcoretcpdphy-refé~ùúð€ª•”L%uphyuphy-pipeuphy-tcphy¸ ðokayû/dp-port ÁG4usb3-port ÁG1phy@ff800000rockchip,rk3399-typec-phyÃÿ€è€ätcpdcoretcpdphy-refé€ùúð€ª �œM%uphyuphy-pipeuphy-tcphy¸  ðdisableddp-port Áusb3-port ÁG3watchdog@ff848000 rockchip,rk3399-wdtsnps,dw-wdtÃÿ„€è|=xrktimer@ff850000rockchip,rk3399-timerÃÿ…=QèhZ äpclktimerspdif@ff870000rockchip,rk3399-spdifÃÿ‡=B�`”tx ämclkhclkèUת¨ðokayGÖi2s@ff880000(rockchip,rk3399-i2srockchip,rk3066-i2sÃÿˆ¸ ='�``”txrxäi2s_clki2s_hclkèVÔ:defaultH•ª¨ðokayGÕi2s@ff890000(rockchip,rk3399-i2srockchip,rk3066-i2sÃÿ‰=(�``”txrxäi2s_clki2s_hclkèWÕ:defaultH–ª¨ ðdisabledi2s@ff8a0000(rockchip,rk3399-i2srockchip,rk3066-i2sÃÿŠ=)�``”txrxäi2s_clki2s_hclkèXÖª¨ ðdisabledG©vop@ff8f0000rockchip,rk3399-vop-litÃÿ�>ü=wéÛÛùׄõáèÛµÛäaclk_vopdclk_vophclk_vop G—ª %axiahbdclkðokayport+Gendpoint@0ù˜G®endpoint@1ù™G¼endpoint@2ùšG¬endpoint@3ù›G¸endpoint@4ùœG6iommu@ff8f3f00rockchip,iommuÃÿ�?=wèÛÛ äaclkifaceª NðokayG—vop@ff900000rockchip,rk3399-vop-bigÃÿ�>ü=véÙÙùׄõáèÙ´Ùäaclk_vopdclk_vophclk_vop G�ª %axiahbdclkðokayport+Gendpoint@0ùžG»endpoint@1ùŸG­endpoint@2ù G«endpoint@3ù¡G·endpoint@4ù¢G5iommu@ff903f00rockchip,iommuÃÿ�?=vèÙÙ äaclkifaceª NðokayG�isp0@ff910000rockchip,rk3399-cif-ispÃÿ‘@=+ènéãäispaclkhclk G£¤ dphyªðokayports+port@0Ã+endpoint@0ù¥mGFendpoint@1ù¦mGHiommu@ff914000rockchip,iommu Ãÿ‘@ÿ‘P=+èéã äaclkiface Nª àðokayG£isp1@ff920000rockchip,rk3399-cif-ispÃÿ’@=,èoêääispaclkhclk G§¨ dphyª ðdisabledports+port@0Ã+iommu@ff924000rockchip,iommu Ãÿ’@ÿ’P=,èêä äaclkiface Nª àG§hdmi-soundsimple-audio-card ûi2s  .hdmi-sound ðdisabledsimple-audio-card,cpu E©simple-audio-card,codec Eªhdmi@ff940000rockchip,rk3399-dw-hdmiÃÿ”=(ètqpoäiahbisfrcecgrfrefª‚¸ ¨ ðdisabledGªportsport+endpoint@0ù«G endpoint@1ù¬Gšmipi@ff960000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsiÃÿ–€=- è¢p£oärefpclkphy_cfggrfªû%apb¸ +ðokay Oports+port@0Ã+endpoint@0ù­GŸendpoint@1ù®G˜port@1Ãendpoint¹¯Gµpanel@0à \° f±:defaultH²innolux,p097pfgH³ s´ports+port@0Ãendpoint¹µG¯port@1Ãendpoint@1¹¶G¹mipi@ff968000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsiÃÿ–€€=. è¢q¤oärefpclkphy_cfggrfªü%apb¸ + ÁðokayG¨ports+port@0Ã+endpoint@0ù·G¡endpoint@1ù¸G›port@1Ãendpoint¹¹G¶edp@ff970000rockchip,rk3399-edpÃÿ—€= èjlo ädppclkgrf:defaultHºª%dp¸  ðdisabledports+port@0Ã+endpoint@0ù»Gžendpoint@1ù¼G™gpu@ff9a0000#rockchip,rk3399-maliarm,mali-t860Ãÿš0= ÀjobmmugpuèÐïª#ðokay(½ ¾Gjpinctrlrockchip,rk3399-pinctrl¸ È+:default H¿ÀÁgpio@ff720000rockchip,gpio-bankÃÿrè‚= ‹ ›•™â §CLK_32K_APEC_IN_RW_ODSPK_PA_ENWLAN_PERST_1V8_LWLAN_PD_1V8_LWLAN_RF_KILL_1V8_LBIGCPU_DVS_PWMSD_CD_L_JTAG_ENBT_EN_BT_RF_KILL_1V8_LPMUIO2_33_18_L_PP3300_S0_ENTOUCH_RESET_LAP_EC_WARM_RESET_REQPEN_RESET_LAP_FLASH_WP_LGgpio@ff730000rockchip,gpio-bankÃÿsè‚= ‹ ›•™‰ §PEN_INT_ODLPEN_EJECT_ODLBT_HOST_WAKE_1V8_LWLAN_HOST_WAKE_1V8_LTOUCH_INT_ODLAP_EC_S3_S0_LAP_EC_OVERTEMPAP_SPI_FLASH_MISOAP_SPI_FLASH_MOSI_RAP_SPI_FLASH_CLK_RAP_SPI_FLASH_CS_L_RSD_CARD_DET_ODLAP_EXPANSION_IO1AP_EXPANSION_IO2AP_I2C_DISP_SDAAP_I2C_DISP_SCLH1_INT_ODLEC_AP_INT_ODLLITCPU_DVS_PWMAP_I2C_AUDIO_SDAAP_I2C_AUDIO_SCLAP_EXPANSION_IO3HEADSET_INT_ODLAP_EXPANSION_IO4G&gpio@ff780000rockchip,gpio-bankÃÿxèP= ‹ ›•™  §AP_I2C_PEN_SDAAP_I2C_PEN_SCLSD_IO_PWR_ENUCAM_RST_LPP1250_CAM_ENWCAM_RST_LAP_EXPANSION_IO5AP_I2C_CAM_SDAAP_I2C_CAM_SCLAP_H1_SPI_MISOAP_H1_SPI_MOSIAP_H1_SPI_CLKAP_H1_SPI_CS_LUART_EXPANSION_TX_AP_RXUART_AP_TX_EXPANSION_RXUART_EXPANSION_RTS_AP_CTSUART_AP_RTS_EXPANSION_CTSAP_SPI_EC_MISOAP_SPI_EC_MOSIAP_SPI_EC_CLKAP_SPI_EC_CS_LPP2800_CAM_ENCLK_24M_CAMWLAN_PCIE_CLKREQ_1V8_LSD_PWR_3000_1800_LGEgpio@ff788000rockchip,gpio-bankÃÿx€èQ= ‹ ›•™‚ §I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDI_0STRAP_LCDBIAS_LSTRAP_FEATURE_1STRAP_FEATURE_2I2S0_SDO_0gpio@ff790000rockchip,gpio-bankÃÿyèR= ‹ ›•™Ü §I2S_MCLKAP_I2C_EXPANSION_SDAAP_I2C_EXPANSION_SCLDMIC_ENAP_I2C_TS_SDAAP_I2C_TS_SCLGPU_DVS_PWMUART_DBG_TX_AP_RXUART_AP_TX_DBG_RXBL_ENBL_PWMDISPLAY_RST_LPPVARP_LCD_ENPPVARN_LCD_ENSD_SLOT_PWR_ENG±pcfg-pull-up ·GÆpcfg-pull-down ÄGÈpcfg-pull-none ÓGÂpcfg-pull-none-12ma Ó à GÄpcfg-pull-none-13ma Ó à GÃpcfg-pull-none-18ma Ó àpcfg-pull-none-20ma Ó àpcfg-pull-up-2ma · àpcfg-pull-up-8ma · àpcfg-pull-up-18ma · àpcfg-pull-up-20ma · àpcfg-pull-down-4ma Ä àpcfg-pull-down-8ma Ä àpcfg-pull-down-12ma Ä à pcfg-pull-down-18ma Ä àpcfg-pull-down-20ma Ä àpcfg-output-high ïGÉpcfg-output-low ûpcfg-input-enable pcfg-input-pull-up  · àpcfg-input-pull-down  Ä àclockclk-32k ÂGÀcifcif-clkin  Âcif-clkouta  Âedpedp-hpd ÂGºgmacrgmii-pinsð à à  ÂÂÂÂÃÃÂÂÃÃrmii-pins    à   ÂÂÂÂÃÃi2c0i2c0-xfer ÂÂGˆi2c1i2c1-xfer ÂÂG7i2c2i2c2-xfer ÄÄG8i2c3i2c3-xfer ÂÂG;i2c4i2c4-xfer   ÂG‰i2c5i2c5-xfer   ÂG>i2c6i2c6-xfer   ÂG?i2c7i2c7-xfer ÂÂG@i2c8i2c8-xfer ÂÂGŠi2s0i2s0-2ch-bus` ÂÂÂÂÂÂi2s0-8ch-bus` ÅÅÅÅÅÅG•i2s1i2s1-2ch-busP ÂÂÂÂÂG–sdio0sdio0-bus1 Æsdio0-bus4@ ÆÆÆÆsdio0-cmd Æsdio0-clk Âsdio0-cd Æsdio0-pwr Æsdio0-bkpwr Æsdio0-wp Æsdio0-int Æsdmmcsdmmc-bus1 Æsdmmc-bus4@ Ç Ç Ç ÇG%sdmmc-clk  ÇG!sdmmc-cmd  ÇG"sdmmc-cd ÂG#sdmmc-wp Æsdmmc-cd-pin  ÆG$suspendap-pwroff ÂG¿ddrio-pwroff Âspdifspdif-bus Âspdif-bus-1 Âspi0spi0-clk ÆGNspi0-cs0 ÆGQspi0-cs1 Æspi0-tx ÆGOspi0-rx ÆGPspi1spi1-clk  ÆGRspi1-cs0  ÆGUspi1-rx ÆGTspi1-tx ÆGSspi1-sleep@  È ÈÈÈGVspi2spi2-clk  ÆGWspi2-cs0  ÆGZspi2-rx  ÆGYspi2-tx  ÆGXspi3spi3-clk ÆGƒspi3-cs0 ÆG†spi3-rx ÆG…spi3-tx ÆG„spi4spi4-clk ÆG\spi4-cs0 ÆG_spi4-rx ÆG^spi4-tx ÆG]spi5spi5-clk ÆGaspi5-cs0 ÆGdspi5-rx ÆGcspi5-tx ÆGbtestclktest-clkout0 Âtest-clkout1 ÂGAtest-clkout2 Âtsadcotp-pin ÂGkotp-out ÂGluart0uart0-xfer ÆÂGIuart0-cts Âuart0-rts Âuart1uart1-xfer  Æ ÂGJuart2auart2a-xfer Æ Âuart2buart2b-xfer ÆÂuart2cuart2c-xfer ÆÂGKuart3uart3-xfer ÆÂGLuart3-cts Âuart3-rts Âuart4uart4-xfer ÆÂG‡uarthdcpuarthdcp-xfer ÆÂpwm0pwm0-pin ÂG�pwm0-pin-pull-down Èvop0-pwm-pin Âvop1-pwm-pin Âpwm1pwm1-pin ÂGŽpwm1-pin-pull-down Èpwm2pwm2-pin ÂG�pwm2-pin-pull-down Èpwm3apwm3a-pin ÂG�pwm3bpwm3b-pin Âhdmihdmi-i2c-xfer ÂÂhdmi-cec Âpciepci-clkreqn-cpm ÂGpci-clkreqnb-cpm Âpcfg-pull-none-8ma Ó àGÇbacklight-enablebl-en ÂGãcros-ecec-ap-int-l ÆGediscrete-regulatorssd-io-pwr-en ÂGÒsd-pwr-1800-sel ÆGÓsd-slot-pwr-en ÂGÑdisplay-rst-l ÈG²ppvarp-lcd-en ÂGÞppvarn-lcd-en ÂGÝcodecheadset-int-l ÆG‹mic-int  Èmax98357asdmode-en ÈGÔtouchscreentouch-int-l ÈG<touch-reset-l  ÈG=trackpadap-i2c-tp-pu-en  Étrackpad-int-l Æwifiwlan-module-reset-l  Âbt-host-wake-l ÂG,bt-en-1v8-l ÂGàwlan-pd-1v8-l ÂGáwlan-rf-kill-1v8-l ÆGÁwifi-perst-l ÂGwlan-host-wake-l Æwrite-protectap-fw-wp  Âpcfg-pull-none-6ma Ó àGÅcamerapp1250-dvdd ÂGÛpp2800-avdd ÂGßucam_rst ÂGGwcam_rst ÂGBdigitizerpen-int-odl ÆG9pen-reset-l  ÂG:dmicdmic-en ÂGåpenpen-eject-odl ÆGætpmh1-int-od-l ÆG[opp-table-0operating-points-v2 !G opp00 ,Q– 3 5 Aœ@opp01 ,#ÃF 3 –¨opp02 ,0£, 3 øPopp03 ,<Ü 3 » opp04 ,G†Œ 3à˜opp05 ,Tfr 3Èà Ropp06 ,ZJ 3Œ0opp-table-1operating-points-v2 !G opp00 ,Q– 3 5 Aœ@opp01 ,#ÃF 3 5opp02 ,0£, 3 –¨opp03 ,<Ü 3 øPopp04 ,G†Œ 3 » opp05 ,Tfr 3à˜opp06 ,_Ø" 3� Ropp07 ,kIÒ 3Œ0opp08 ,x)¸ 3Ðopp-table-2operating-points-v2G½opp00 , ë 3 5opp01 ,³Ü@ 3 5opp02 ,ׄ 3 –¨opp03 ,Íe 3 øPopp04 ,#ÃF 3Hopp05 ,/¯ 3g8dmc_opp_tableoperating-points-v2Gopp00 ,ׄ 3 » opp01 ,'²Z€ 3 » opp02 ,/¯ 3 » opp03 ,7P( 3 »  Rchosen ^serial2:115200n8ppvar-sysregulator-fixed jppvar_sys y �GÊpp1200-lpddrregulator-fixed jpp1200_lpddr y � ŸO€ ·O€ ÏÊpp1800regulator-fixed jpp1800 y � Ÿw@ ·w@ ÏÊGpp3300regulator-fixed jpp3300 y � Ÿ2Z  ·2Z  ÏÊGŒpp5000regulator-fixed jpp5000 y � ŸLK@ ·LK@ ÏÊppvar-bigcpu-pwmpwm-regulator jppvar_bigcpu_pwm ÚË  ßÊ êd þd y � Ÿ 5J ·ÓGÌppvar-bigcpuvctrl-regulator jppvar_bigcpu Ÿ 5J ·Ó Ì  5JÓ 0BGppvar-litcpu-pwmpwm-regulator jppvar_litcpu_pwm ÚÍ  ßÊ êd þd y � Ÿ =J ·NGÎppvar-litcpuvctrl-regulator jppvar_litcpu Ÿ =J ·N Î  =JN 0€G ppvar-gpu-pwmpwm-regulator jppvar_gpu_pwm ÚÏ  ßÊ êd þd y � Ÿ 3p ·ÇPGÐppvar-gpuvctrl-regulator jppvar_gpu Ÿ 3p ·ÇP Ð  3pÇP 0†G¾pp900-appp3000-sd-slotregulator-fixed jpp3000_sd_slot:defaultHÑ N a± ÏŒG'ppvar-sd-card-ioregulator-gpio jppvar_sd_card_io:defaultHÒÓ N fE 4E!w@2Z  Ÿw@ ·2Z G(pp3300-trackpadap-rtc-clk fixed-clock_€oxin32k‚max98357amaxim,max98357a:defaultHÔ r ¨ðokayG×soundrockchip,rk3399-gru-sound ŒÕÖ ™×ØÙÚpp1250-s3regulator-fixed jpp1250_s3 y � ŸÐ ·Ð ÏÊGÜpp1250-dvddregulator-fixed jpp1250_dvdd:defaultHÛ N aE ¨è ÏÜGDpp900-s0regulator-fixed jpp900_s0 y � Ÿ »  · »  ÏÊGppvarn-lcdregulator-fixed jppvarn_lcd:defaultHÝ N a± ÏÊG´ppvarp-lcdregulator-fixed jppvarp_lcd:defaultHÞ N a± ÏÊG³pp900-s3regulator-fixed jpp900_s3 y � Ÿ »  · »  Ïpp2800-avddregulator-fixed jpp2800_avdd:defaultHß N aE ¨d ÏŒGCbt-3v3regulator-fixed jbt_3v3:defaultHà N a ÏŒGâwlan-3v3regulator-fixed jwlan_3v3:defaultHá N a ¹' ÏâGbacklightpwm-backlight f±:defaultHã ÚäB@ Õ'G°dmic dmic-codec â±:defaultHå ïúGØgpio-keys gpio-keys:defaultHæpen-insert ÿPen Insert 4&! compatibleinterrupt-parent#address-cells#size-cellschassis-typemodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4mmc0mmc1cpudevice_typeregenable-methodcapacity-dmips-mhzclocks#cooling-cellsdynamic-power-coefficientcpu-idle-statesoperating-points-v2cpu-supplyphandleduration-usexit-latency-usentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usmin-residency-usportsrockchip,pmudevfreq-eventsclock-namesstatusrockchip,pd-idle-nsrockchip,sr-idle-nsrockchip,sr-mc-gate-idle-nsrockchip,srpd-lite-idle-nsrockchip,standby-idle-nsrockchip,ddr3_odt_dis_freqrockchip,lpddr3_odt_dis_freqrockchip,lpddr4_odt_dis_freqrockchip,sr-mc-gate-idle-dis-freq-hzrockchip,srpd-lite-idle-dis-freq-hzrockchip,standby-idle-dis-freq-hzcenter-supplyinterruptsarm,no-tick-in-suspendclock-frequencyclock-output-names#clock-cellsreg-names#interrupt-cellsaspm-no-l0sbus-rangeinterrupt-namesinterrupt-map-maskinterrupt-mapmax-link-speedmsi-mapphysphy-namesrangesresetsreset-namesep-gpiospinctrl-namespinctrl-0vpcie3v3-supplyvpcie1v8-supplyvpcie0v9-supplypcie-reset-suspendinterrupt-controllerpower-domainsrockchip,grfsnps,txpblmax-frequencyfifo-depthassigned-clocksassigned-clock-ratesbus-widthcap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplyarasan,soc-ctl-syscondisable-cqe-dcmdmmc-hs400-1_8vmmc-hs400-enhanced-strobenon-removableextcondr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirk#sound-dai-cellsremote-endpointmsi-controller#msi-cellsaffinity#io-channel-cellsi2c-scl-falling-time-nsi2c-scl-rising-time-nshid-descr-addrreset-gpiosavdd-supplydvdd-supplydovdd-supplydata-lanesreg-shiftreg-io-widthdmasdma-namespinctrl-1spi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countgoogle,usb-port-idkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymappolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#power-domain-cellspm_qospmu1830-supplydlg,micbias-lvldlg,mic-amp-in-selVDD-supplyVDDMIC-supplyVDDIO-supplydlg,adc-1bit-rptdlg,btn-avgdlg,btn-cfgdlg,mic-det-thrdlg,jack-ins-debdlg,jack-det-ratedlg,jack-rem-debdlg,a-d-btn-thrdlg,d-b-btn-thrdlg,b-c-btn-thrdlg,c-mic-btn-thr#pwm-cellsiommus#iommu-cells#dma-cellsarm,pl330-periph-burst#reset-cellsaudio-supplybt656-supplygpio1830-supplysdmmc-supply#phy-cellsdrive-impedance-ohmrockchip,disable-mmu-resetsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namesound-daiclock-masterbacklightenable-gpiosavee-supplymali-supplygpio-controller#gpio-cellsgpio-line-namesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplypwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitctrl-supplyctrl-voltage-rangeregulator-settling-time-up-usenable-active-highgpioenable-gpiosdmode-gpiossdmode-delayrockchip,cpurockchip,codecstartup-delay-usregulator-enable-ramp-delaypwm-delay-usdmicen-gpioswakeup-delay-mslabellinux,codelinux,input-typewakeup-source