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#pwmpclk&defaultˆ ^disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0 0 #pwmpclk'defaultˆ ^disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controller“ I power-domain@7  §(“power-domain@8 Ì Í §)*+“power-domain@9  Ú Û Ü §,-.“power-domain@10  ñ ò§/01234“power-domain@11  í§5“power-domain@13  §6“power-domain@14  §789“power-domain@15 §:;<=>“gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$¬()' ®jobmmugpu #gpubus *?P  ^disabledI�mmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ ¬d  Á  Ž �#biuciuciu-driveciu-sample¾ÉðÑ€v ë×reset ^disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ¬ ®macirqeth_wake_irq@ † ‰ ‰ Ç Ã Ä ‰ ÈW#stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refv ì ×stmmaceth¥ã@óAB*^okay€ ‰ ‡ †3 ‡ †CJinputWrgmii`defaultDEFGHI kJ{ ‘N † ¦O¯$¸Kmdio,snps,dwmac-mdio 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Y#pdm_clkpdm_hclklV îrxdefghidefaultv X×pdm-mø ^disableddma-controller@fe530000,arm,pl330arm,primecellþS@¬     #apb_pclk I"dma-controller@fe550000,arm,pl330arm,primecellþU@¬    #apb_pclk IVi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ ¬/ H G #i2cpclkjdefault  ^disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ ¬0 J I #i2cpclkkdefault ^okayi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ ¬1 L K #i2cpclkldefault ^okayi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] ¬2 N M #i2cpclkmdefault ^okayi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ ¬3 P O #i2cpclkndefault  ^disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` ¬•   #tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa ¬g R Q#spiclkapb_pclkl""îtxrxdefault opq  ^disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb ¬h T S#spiclkapb_pclkl""îtxrxdefault rst  ^disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc ¬i V U#spiclkapb_pclkl""îtxrxdefault uvw  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^disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ] \ #pwmpclk•defaultˆ ^disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ] \ #pwmpclk–defaultˆ ^disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo  ] \ #pwmpclk—defaultˆ ^disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0 ] \ #pwmpclk˜defaultˆ ^disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp ` _ #pwmpclk™defaultˆ ^disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp ` _ #pwmpclkšdefaultˆ ^disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp  ` _ #pwmpclk›defaultˆ ^disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0 ` _ #pwmpclkœdefaultˆ ^disabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ" }  #refapbpipe€"�õáv Ç G� Yž o^okayI phy@fe840000,rockchip,rk3568-naneng-combphyþ„% ~  #refapbpipe€%�õáv É G� YŸ o ^disabledIusb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠ#phyclkñclk_usbphy0_480m ¬‡ z Ÿ^okayIhost-port o^okay`¡Iotg-port o^okay`¢Iusb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹#phyclkñclk_usbphy1_480m ¬ˆ z£Ÿ^okayhost-port o ^disabledIotg-port o^okay`¡Ipinctrl,rockchip,rk3568-pinctrl¥ Ф gpio@fdd60000,rockchip,gpio-bankýÖ ¬!.  — §«ÀIgpio@fe740000,rockchip,gpio-bankþt ¬" c d — §«Àgpio@fe750000,rockchip,gpio-bankþu ¬# e f — §«Àgpio@fe760000,rockchip,gpio-bankþv ¬$ g h — §«ÀIJgpio@fe770000,rockchip,gpio-bankþw ¬% i j — §«Àpcfg-pull-up ³I§pcfg-pull-down ÀI­pcfg-pull-none ÏI¥pcfg-pull-none-drv-level-1 Ï ÜI©pcfg-pull-none-drv-level-2 Ï ÜI¨pcfg-pull-none-drv-level-3 Ï ÜI¬pcfg-pull-up-drv-level-1 ³ ÜI«pcfg-pull-up-drv-level-2 ³ ÜI¦pcfg-pull-none-smt Ï ëIªacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 ¥I cpuebcedpdpemmceth0eth1flashfspifspi-pins` ¥¥¥¥¥¥IUgmac0gmac1gmac1m1-miim ¥¥IDgmac1m1-clkinout ¥IHgmac1m1-rx-bus20 ¥¥ ¥IFgmac1m1-tx-bus20 ¨¨¥IEgmac1m1-rgmii-clk ¥©IGgmac1m1-rgmii-bus@ ¥¥¨¨IIgpuhdmitxi2c0i2c0-xfer ª ªIi2c1i2c1-xfer ª ªIji2c2i2c2m1-xfer  ª ªIki2c3i2c3m1-xfer  ªªIli2c4i2c4m0-xfer  ª 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interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendarm,smc-idshmem#clock-cellsinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsstatusdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supplyregulator-off-in-suspendrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-init-microvoltregulator-on-in-suspendregulator-suspend-microvoltregulator-initial-modedmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesfifo-depthmax-frequencyreset-namessnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoassigned-clock-parentsclock_in_outphy-modephy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlesnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usebus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablespi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthmmc-hs200-1_8vdma-names#sound-dai-cellsarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosvbat-supplyvddio-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathlabeldefault-statelinux,default-triggerretain-state-suspendedreset-gpiospost-power-on-delay-mspower-off-delay-usenable-active-high