Ð þí¼�8²|( ²D ,radxa,rock3arockchip,rk35687Radxa ROCK3 Model Aaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe010000ç/mmc@fe2b0000ì/mmc@fe310000cpus cpu@0ñcpu,arm,cortex-a55ýpsci%9Dcpu@100ñcpu,arm,cortex-a55ýpsci%9Dcpu@200ñcpu,arm,cortex-a55ýpsci%9Dcpu@300ñcpu,arm,cortex-a55ýpsci%9D opp-table-0,operating-points-v2LDopp-408000000WQ– ^ »  » Œ0lœ@opp-600000000W#ÃF ^ »  » Œ0opp-816000000W0£, ^ »  » Œ0}opp-1104000000WAÍ´ ^ »  » Œ0opp-1416000000WTfr ^ »  » Œ0opp-1608000000W_Ø" ^à˜à˜Œ0opp-1800000000WkIÒ ^��Œ0opp-1992000000Wv»‚ ^Œ0Œ0Œ0firmwarescmi ,arm,scmi-smc‰‚” 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™p!qDDregulator-state-memADCDC_REG3¼vcc_ddrËß6regulator-state-memMDCDC_REG4¼vdd_npu » 6ñ¡  ™p!qregulator-state-memADCDC_REG5¼vcc_1v8Ëßñw@ w@Dregulator-state-memALDO_REG1¼vdda0v9_imageñ »  » regulator-state-memALDO_REG2 ¼vdda_0v9Ëßñ »  » regulator-state-memALDO_REG3 ¼vdda0v9_pmuËßñ »  » regulator-state-memMe » LDO_REG4 ¼vccio_acodecËñ2Z  2Z Dregulator-state-memALDO_REG5 ¼vccio_sdñw@ 2Z Dregulator-state-memALDO_REG6 ¼vcc3v3_pmuËßñ2Z  2Z Dregulator-state-memMe2Z LDO_REG7 ¼vcca_1v8Ëßñw@ w@DŽregulator-state-memALDO_REG8 ¼vcca1v8_pmuËßñw@ w@regulator-state-memMew@LDO_REG9¼vcca1v8_imageñw@ w@regulator-state-memASWITCH_REG1¼vcc_3v3ËßDregulator-state-memASWITCH_REG2 ¼vcc3v3_sdDTregulator-state-memAcodec�serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýýÕ §t ,baudclkapb_pclk•##ÿ$ defaultš§ Ydisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmýý× 0 pwmpclkÿ% default± Ydisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmýý× 0 pwmpclkÿ& default± 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ethernet-phy@0,ethernet-phy-ieee802.3-c22ý defaultÿN‰N ™†  «ODHstmmac-axi-config·ÁÑDErx-queues-configáDFqueue0tx-queues-config÷DGqueue0qos@fe128000,rockchip,rk3568-qossysconýþ€ D)qos@fe138080,rockchip,rk3568-qossysconýþ€€ D8qos@fe138100,rockchip,rk3568-qossysconýþ� D9qos@fe138180,rockchip,rk3568-qossysconýþ�€ D:qos@fe148000,rockchip,rk3568-qossysconýþ€ D*qos@fe148080,rockchip,rk3568-qossysconýþ€€ D+qos@fe148100,rockchip,rk3568-qossysconýþ� D,qos@fe150000,rockchip,rk3568-qossysconýþ D6qos@fe158000,rockchip,rk3568-qossysconýþ€ D0qos@fe158100,rockchip,rk3568-qossysconýþ� D1qos@fe158180,rockchip,rk3568-qossysconýþ�€ D2qos@fe158200,rockchip,rk3568-qossysconýþ‚ D3qos@fe158280,rockchip,rk3568-qossysconýþ‚€ D4qos@fe158300,rockchip,rk3568-qossysconýþƒ D5qos@fe180000,rockchip,rk3568-qossysconýþ qos@fe190000,rockchip,rk3568-qossysconýþ D;qos@fe190280,rockchip,rk3568-qossysconýþ€ D?qos@fe190300,rockchip,rk3568-qossysconýþ D@qos@fe190380,rockchip,rk3568-qossysconýþ€ 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Ydisabledpdm@fe440000,rockchip,rk3568-pdmýþD §L Z Ypdm_clkpdm_hclk•Z qrxÿhijklm defaultq X pdm-m’ Ydisableddma-controller@fe530000,arm,pl330arm,primecellýþS@§ –   apb_pclk­D#dma-controller@fe550000,arm,pl330arm,primecellýþU@§–   apb_pclk­DZi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþZ §/ H G i2cpclkÿn default  Ydisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ[ §0 J I i2cpclkÿo default  Ydisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ\ §1 L K i2cpclkÿp default  Ydisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ] §2 N M i2cpclkÿq default  Ydisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cýþ^ §3 P O i2cpclkÿr default  Ydisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtýþ` §•   tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiýþa §g R Qspiclkapb_pclk•##qtxrx default ÿstu  Ydisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiýþb §h T Sspiclkapb_pclk•##qtxrx default ÿvwx  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¨Dni2c2i2c2m0-xfer i ¨¨Doi2c3i2c3m0-xfer i¨¨Dpi2c4i2c4m0-xfer i ¨ ¨Dqi2c5i2c5m0-xfer i ¨ ¨Dri2s1i2s1m0-lrckrx i£D_i2s1m0-lrcktx i£D^i2s1m0-mclk i£D!i2s1m0-sclkrx i£D]i2s1m0-sclktx i£D\i2s1m0-sdi0 i £D`i2s1m0-sdi1 i £Dai2s1m0-sdi2 i £Dbi2s1m0-sdi3 i£Dci2s1m0-sdo0 i£Ddi2s1m0-sdo1 i£Dei2s1m0-sdo2 i £Dfi2s1m0-sdo3 i £Dgi2s2i2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk i£Dhpdmm0-clk1 i£Dipdmm0-sdi0 i £Djpdmm0-sdi1 i £Dkpdmm0-sdi2 i £Dlpdmm0-sdi3 i£Dmpmicpmic_int i¥D pmupwm0pwm0m0-pins i£D%pwm1pwm1m0-pins i£D&pwm2pwm2m0-pins i£D'pwm3pwm3-pins i£D(pwm4pwm4-pins i£D�pwm5pwm5-pins i£D�pwm6pwm6-pins i£D‘pwm7pwm7-pins i£D’pwm8pwm8m0-pins i £D“pwm9pwm9m0-pins i £D”pwm10pwm10m0-pins i £D•pwm11pwm11m0-pins i£D–pwm12pwm12m0-pins i£D—pwm13pwm13m0-pins i£D˜pwm14pwm14m0-pins i£D™pwm15pwm15m0-pins i£Dšrefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ i¤¤¤¤DPsdmmc0-clk i¤DQsdmmc0-cmd i¤DRsdmmc0-det i¥DSsdmmc1sdmmc2spdifspdifm0-tx i£D[spi0spi0m0-pins0 i £££Duspi0m0-cs0 i£Dsspi0m0-cs1 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interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1device_typeregclocks#cooling-cellsenable-methodoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendarm,smc-idshmem#clock-cellsinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsstatusdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendassigned-clock-parentsrockchip,system-power-controller#sound-dai-cellsvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-init-microvoltregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltmic-in-differentialdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyfifo-depthmax-frequencyreset-namessnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modereset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usebus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplynon-removabledma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplyvbus-supplyrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathfunctioncolorlinux,default-triggersimple-audio-card,formatsimple-audio-card,namesimple-audio-card,mclk-fssound-daienable-active-highgpio