Ð þí5d81À(¤1ˆ&Microchip PolarFire-SoC Discovery KitU!microchip,mpfs-disco-kit-reference-rtl-v2507microchip,mpfs-disco-kitmicrochip,mpfscpus,B@cpu@0 !sifive,e51sifive,rocket0riscv?cpuK@^€k@x |rv64imac†rv64i$•imaczicntrzicsrzifenceizihpmª ±disabled¸interrupt-controllerÀ!riscv,cpu-intcѸ cpu@1#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸ cpu@2#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸ cpu@3#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸ cpu@4#!sifive,u54-mcsifive,rocket0riscvæ@ù@€ ?cpuK@^@k€)4  ?riscv,sv39x |rv64imafdc†rv64i(•imafdczicntrzicsrzifenceizihpmªHR±okay¸interrupt-controllerÀ!riscv,cpu-intcѸcpu-mapcluster0core0ccore1ccore2ccore3ccore4cmssrefclk !fixed-clockgtsY@¸syscontroller!microchip,mpfs-sys-controller„±okaymssclkclk !fixed-clockgtÄ´¸soc !simple-bus‹cache-controller@20100005!microchip,mpfs-ccachesifive,fu540-c000-ccachecachexM@’`m ž¬ ½¸clint@2000000&!sifive,fu540-c000-clintsifive,clint0xÀPÈ        interrupt-controller@c000000)!sifive,fu540-c000-plicsifive,plic-1.0.0x ÀÑHÈ   ܺ¸ dma-controller@3000000!!microchip,mpfs-pdmasifive,pdma0x€¬  ½ çôsyscon@200020000!microchip,mpfs-mss-top-sysregsysconsimple-mfdx ÿ¸syscon@20003000!!microchip,mpfs-sysreg-scbsysconx 0clock-controller@38010000!microchip,mpfs-ccc@x8899g ±disabledclock-controller@38040000!microchip,mpfs-ccc@x8899g ±disabledclock-controller@38100000!microchip,mpfs-ccc@x88 99 g ±disabledclock-controller@38400000!microchip,mpfs-ccc@x8@8€9@9€g±okayª: pll0_ref0pll0_ref1pll1_ref0pll1_ref1dll0_refdll1_ref¸serial@20000000 !ns16550ax %¬ ½Z/ª ±disabledserial@20100000 !ns16550ax %¬ ½[/ª ±okayserial@20102000 !ns16550ax  %¬ ½\/ª  ±disabledserial@20104000 !ns16550ax @%¬ ½]/ª  ±disabledserial@20106000 !ns16550ax `%¬ ½^ª /±okaymmc@20008000 !microchip,mpfs-sd4hccdns,sd4hcx €¬ ½Xª= ë±okayKU`qƒ��ª¸spi@20108000!microchip,mpfs-spix €¬ ½6ª ±okayspi@20109000!microchip,mpfs-spix �¬ ½7ª±okayspi@21000000.!microchip,mpfs-qspimicrochip,coreqspi-rtl-v2x!¬ ½Uª ±disabledi2c@2010a000,!microchip,mpfs-i2cmicrochip,corei2c-rtl-v7x  ¬ ½:ªt† ±okayi2c@2010b000,!microchip,mpfs-i2cmicrochip,corei2c-rtl-v7x °¬ ½=ªt†  ±disabledcan@2010c000!microchip,mpfs-canx Àª%¬ ½8Á ±disabledcan@2010d000!microchip,mpfs-canx Ъ%¬ ½9Á ±disabledethernet@20110000!microchip,mpfs-macbcdns,macbx  ¬ ½@ABCDEȪ  pclkhclkÁ±okayÚsgmiiãethernet-phy@bx ¸ethernet@20112000!microchip,mpfs-macbcdns,macbx  ¬ ½FGHIJKȪ  pclkhclkÁ ±disabledgpio@20120000!microchip,mpfs-gpiox ¬ ÑÀªîþ ±disabledgpio@20121000!microchip,mpfs-gpiox ¬ ÑÀªîþ±okay`½ !/#$%&'()*+,-./012¸gpio@20122000!microchip,mpfs-gpiox  ¬ ÑÀªîþ±okay€½55555555555555555555555555555555¸rtc@20124000!microchip,mpfs-rtcx @¬ ½PQª!  rtcrtcref±okayusb@20201000!microchip,mpfs-musbx ¬ ½VWª dmamc ±disabledsyscon@37020000"!microchip,mpfs-control-scbsysconx7mailbox@37020800!microchip,mpfs-mailboxx7¬ ½`±okay¸spi@37020100.!microchip,mpfs-qspimicrochip,coreqspi-rtl-v2x7¬ ½nª ±disabledclkcfg@3e001000!microchip,mpfs-clkcfgx>ªg¸pwm@40000000!microchip,corepwm-rtl-v4x@ð&Aª±okayi2c@40000200!microchip,corei2c-rtl-v7x@ª¬ ½zt† ±okaymailbox!microchip,sbi-ipc¬ ½´³²± hart-1hart-2hart-3hart-4±okaymailbox@50000000!microchip,miv-ihc-rtl-v2xPÀ¬ ½´³²± hart-1hart-2hart-3hart-4L ±disabledclock-cccref !fixed-clockgtúð€¸aliasesm/soc/ethernet@20110000w/soc/serial@20106000chosenserial4:115200n8leds !gpio-ledsled-1 ‹‘—led1led-2 ‹‘—led2led-3 ‹‘—led3led-4 ‹‘—led4led-5 ‹‘—led5led-6 ‹‘—led6led-7 ‹‘—led7led-8 ‹ ‘—led8memory@80000000?memoryx€@reserved-memory‹region@bfc00000x¿À@� #address-cells#size-cellsmodelcompatibletimebase-frequencydevice_typei-cache-block-sizei-cache-setsi-cache-sizeregriscv,isariscv,isa-baseriscv,isa-extensionsclocksstatusphandle#interrupt-cellsinterrupt-controllerd-cache-block-sized-cache-setsd-cache-sized-tlb-setsd-tlb-sizei-tlb-setsi-tlb-sizemmu-typetlb-splitnext-level-cachecpu#clock-cellsclock-frequencymboxesrangescache-levelcache-unifiedinterrupt-parentinterruptsinterrupts-extendedriscv,ndevdma-channels#dma-cells#reset-cellsclock-namesreg-io-widthreg-shiftcurrent-speedmax-frequencybus-widthdisable-wpcap-sd-highspeedcap-mmc-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104no-1-8-vresetslocal-mac-addressphy-modephy-handlegpio-controller#gpio-cellsinterrupt-names#mbox-cellsmicrochip,sync-update-mask#pwm-cellsmicrochip,ihc-chan-disabled-maskethernet0serial4stdout-pathgpioscolorlabelno-map